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Politics : Formerly About Advanced Micro Devices

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To: kash johal who wrote (48848)2/7/1999 12:25:00 AM
From: Elmer  Read Replies (1) of 1571813
 
Re: "I think there is only one bus but the memory chips are interleaved. The pin count is NOT increased. You do however have 4 times the memory if you will. So the bus is actually running at 333Mhz. So the bus is not the limiting factor it is DRAM speed.An here they are using slow DRAM."

Kash maybe you can explain what it is about the following statement that confused me into thinking that the bus ran at 83Mhz and had a very high pincount(256 bits)?

techweb.com

"The set provides a 256-bit-wide memory bus running at 83 MHz to support 100-MHz SDRAM."

What is it about this statement that leads you to see something I missed and conclude it actually runs at 333mhz? Now I'm always open to learning new things but I still can't see what I missed here when I concluded it ran at 83Mhz and was 256 bits wide.

EP
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