SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (48856)2/7/1999 4:22:00 AM
From: Tenchusatsu  Read Replies (1) of 1572098
 
<The high pin count causes greater package costs, but the lower bus speed increases yields, and decreases board design issues. The wide K7 bus may turn out to be a lower cost solution than a high speed narrow bus, and yet provide the same performance.>

Yes and no. Higher pin counts does allow for a slower bus which is easier to yield, but that only means you're shifting the problems of testing and manufacturability to the motherboard, chipsets, and everyone else outside of the processor.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News