SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (49229)2/10/1999 7:44:00 PM
From: Tenchusatsu  Read Replies (2) of 1582938
 
Regarding RDRAM and the number of banks:

Uh, now that I think about it, the concept isn't the same as a cache. OK, never mind the L3 comparison. (Dang Starcraft has been taking away my sleep ...)

Here's the concept behind more banks. If you have several transactions outstanding, you can precharge different banks concurrently, provided that each transaction hits a different bank. The worst case scenario is when all these transactions hit the same bank. Then each transaction will have to wait for the previous one to finish precharging and delivering data before it can start its precharge cycle. With more banks, the worst case scenario will occur less frequently than in a memory system with only two or four banks.

I don't know how many transactions the typical Pentium III uniprocessor system will issue at a time. I do know that it's likely to be bursty, i.e. long periods of idleness broken up by short bursts of several reads and writes clustered together. I also know that if several precharges can occur simultaneously, the bandwidth utilization can be increased.

In short, for a single transaction, latency could be longer for RDRAM than for SDRAM. But for multiple outstanding transactions, the latency of the transactions following the first can be hidden as several precharges take place simultaneously.

Whew. The picture becomes even more complicated once you factor in memory transactions coming from an AGP 4x video card as well.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News