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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (49466)2/13/1999 6:06:00 PM
From: Tenchusatsu  Read Replies (1) of 1582886
 
<The PII/PIII core can only support 2 or 3 outstanding load misses (due to the number of execution units).>

I don't know for sure, but I would guess that the P6 core can go up to more than just two or three outstanding reads or writes. It doesn't depend on the number of execution units because of the out-of-order engine. In other words, you don't send an instruction to the execution unit, then issue the memory access. A good OOO engine will normally have a lot of instructions waiting for those execution units. Some of them, perhaps more than two or three at a time, will need data that doesn't reside in the caches.

And like I said before, the processor isn't the only one issuing transactions to memory. AGP will also be another agent issuing stuff to memory. Given that the better AGP cards out there have at least 16 MB of onboard memory, I would guess that "AGP DMA mode" is used, which means the textures are downloaded from DRAM into local memory as needed. This would mean bursts of very heavy traffic every time the locally-stored textures need to be updated.

Like I said before, this subject is pretty complicated, and I'll bet that most of the people on this thread are thoroughly confused by now. The simplest solution would be to reduce the latency to DRAM, but since that really isn't possible without a big breakthrough in DRAM technology, complexity has to enter the picture.

Tenchusatsu
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