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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (49475)2/13/1999 9:24:00 PM
From: Scumbria  Read Replies (1) of 1582866
 
Ten,

I would guess that the P6 core can go up to more than just two or three outstanding reads or writes. It doesn't depend on the number of execution units because of the out-of-order engine

Execution units stall upon a load miss, so the maximum number of load misses is a direct function of the number of execution units. Out of order execution doesn't change this fundamental principle, because you can't execute until the data is available from the load.

You can also have a number of stores pending in a queue, but store latency does not normally affect performance.

I would guess that "AGP DMA mode" is used, which means the textures are downloaded from DRAM into local memory as needed.

Texture load performance is a function of bandwidth, not latency. K7 systems should excel at this, because of the 256 bit DRAM bus. (A really good video card will provide texture memory on board.)

Scumbria
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