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Politics : Formerly About Advanced Micro Devices
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To: Jim McMannis who wrote (50949)2/25/1999 12:16:00 PM
From: Scumbria  Read Replies (4) of 1572173
 
Jim,

Could the cache be causing a problem, a heat problem?

I have to admit, I find this baffling. An L2 cache (if designed for low power consumption), should not be clocked except during an L1 miss. This only occurs on about 3% of cache accesses, so basically the L2 should be turned off 97% of the time. There shouldn't be any heat problem.

From the outside it appears that the K6-3 architects may have made a fundamental mistake and attempted to be too aggressive in the L2 design.

Scumbria
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