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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (50951)2/26/1999 1:45:00 AM
From: Petz  Read Replies (1) of 1572099
 
Scumbria, re: An L2 cache (if designed for low power consumption), should not be clocked except during an L1 miss. This only occurs on about 3% of cache accesses, so basically the L2 should be turned off 97% of the time. There shouldn't be any heat problem.

This is true, but AMD as a matter of policy finds the "program which generates the most heat" and requires that the K6-3 be stable at its rated frequency and 0.1volt below its rated voltage. There is probably some pathological program code out there that exercises the L2 cache and the FPU on almost every cycle. An FFT on a very large data set should do it.

Petz
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