Amy & Intel Investors - More details (From IDF) concerning MERCED
- STill scheduled to sample in midyear (THIS YEAR !)
- Extended Precision FPU to run at 3 GigaFLOPS !
- Single Precision FPU to run at 6 GigaFLops
"Intel said Merced would hit 3-Gflops extended-precision floating-point performance and 6-Gflops single-precision. "Those two numbers were enough to convince some of my users we made the right move in going with Merced," said John Mashey, director of systems technology at Silicon Graphics Inc. in a panel session here."
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techweb.com
March 01, 1999, Issue: 1050 Section: News
Intel promises that Merced will sample by midyear David Lammers
Palm Springs, Calif. - At the Intel Developer Forum here, Intel Corp. said Merced processor development has reached a milestone: the running of the Unix operating system in a software simulation of a four-way Merced implementation.
The successful interoperability of multiple logic models opens the door for a full-scale push to finish the physical implementation of Merced in time for sampling to OEMs by midyear, said Gadi Singer, an Intel vice president who co-manages the Merced development effort.
System OEMs are receiving the simulation engines now, along with Spice and timing models, so they can debug software concurrently with the chip layout work being done by the hardware team. Besides the seven OSes that are running on the simulation platform, Merced marketing manager Ron Curry said Intel plans to bring up Linux on Merced soon.
Curry said Intel will work with the Linux coordinating council. "The open-source model needs to continue to evolve," he said, adding that Intel believes that technology needs to be developed and tested by companies first, and then shared with the larger community. Some individuals argue that innovations should be shared as they are conceived.
Singer and program co-manager Stephen Smith told reporters that the Intel 460GX chip set, which will support four-way Merced processing, is taping out now. Other system OEMs outside of Intel are developing chip sets to support eight-way and higher levels of multiprocessing.
Floating-point clout
Intel said Merced would hit 3-Gflops extended-precision floating-point performance and 6-Gflops single-precision. "Those two numbers were enough to convince some of my users we made the right move in going with Merced," said John Mashey, director of systems technology at Silicon Graphics Inc. in a panel session here.
Intel promised Merced would handle the RSA encryption algorithm twice as fast as any other processor on the market, but kept mum about performance details overall.
Singer brought a sample of the Merced cartridge to the forum. Level 0 and Level 1 cache are on-chip, but the cartridge will allow L2 cache to communicate across a full-speed bus to the processing elements. Besides the normal heat spreader and fan, Intel is investigating using a heat pipe-essentially a copper pipe with liquid sealed inside-to vector off thermal energy. The goal is to meet the thermal budget of customers, such as Internet service providers, that use rack-mounted servers in a confined space.
Intel fellow John Crawford and Hewlett-Packard senior architect Jerry Huck described how IA-64 will leverage advances in the compiler and instruction set. Branch-specific static prediction and predication techniques will reduce mispredict penalties, while software pipelining will support parallelism, Crawford said.
IA-64 architecture will support data speculation, allowing the compiler to issue a load prior to store and better exception handling. Speculation will boost memory latency 79 percent when combined with predication, important in servers that handle large databases with many accesses to cache, Crawford said.
Copyright ® 1999 CMP Media Inc.
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