SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC)
INTC 43.80+0.7%3:39 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (74956)3/1/1999 2:39:00 PM
From: Tenchusatsu  Read Replies (1) of 186894
 
<Nobody knows how to write a compiler which can take advantage of IA-64's theoretical processing power.>

You sure? I believe there is a lot of communication between compiler writers and Merced-land.

<It is much simpler to write software which partitions the compute tasks at the granularity of the CPU. Attempting to multi-thread a single instruction stream for the APIC architecture, is a ridiculously complex problem.>

Just as ridiculously complex as trying to squeeze out more ILP using a traditional out-of-order RISC-like architecture?

Remember, it's always better to have one processor working twice as fast than to have two processors working at normal speed.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext