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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (51606)3/4/1999 1:49:00 AM
From: Elmer  Read Replies (2) of 1573134
 
Re: "I've seen some very fine speedpath work done using nothing but static timing analysis. There are always ugly sorts of circuit design issues which have to be debugged in silicon, but the advent of C4 bonding is making that increasingly difficult. FIBs and ebeam testing are almost impossible. C4 designs had better flush out most of their speedpaths in simulation."

Yes, with C4 FIBS and EBEAM are no longer useful (after packaging), but there are other methods. Clock stretchers can find vector locations where patterns actually fail, scan based transition fault testing can identify individual critical paths and I understand work is being done to grind down the substrate and sense the fields from the backside, sorry I can't remember the name of this process. Do you know more about this debug methodology?

EP
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