Greg - Re:"... posted to Paul thinking his background could explain it to us non Mit'ers, but I guess Head Killer Intelabee keepeer is busy at the Intelahive." & PMAT
Sorry I've been so busy buzzing around the Intel hive lately - making lots of Honey these days - whoops, that should be Money.
Perhaps the following explanation will help you evaluate PMAT.
PMAT made an announcement about a new process, equipment and
material for depositing thin film dielectrics with a dielectric
constant (k) of about 2, which is quite a bit lower than the
dielectric constant of silicon dioxide/doped oxides, which are
typically about 3.5 +/ 0.3.
For reference, the capacitance between two parallel plate
conductors of equal area, A, separated
by a dielectric (= non-conductor or insulator) is given by:
C = keA/d,
where k = dielectric constant of the insulator
separating the two plates
A = Area of the two plates
d = thickness of the dielectric (= spacing
between the plate conductors.
e = epsilon (my PC won't print Greek letters in Netscape) =
permitivity constant of free space ( a physical constant)
Reducing k lowers the capacitance between two conductors, all
other things assumed constant.
Why is this important?
In IC fabrication, PARASITIC capacitances (i.e, unintentional
but UNAVOIDABLE) slow down circuits, and in severe cases, can
cause signal coupling from one conductor to another. Generally,
this is referred to as noise, and in its most severe cases, will
cause circuit malfunctions.
Speed , Current, & Capacitance
To understand how capacitance affects the speed of circuits,
the simple capacitor equation is a good starting point:
q = CV
q = the electronic charge on a capacitor
C= Capacitance of the Capacitor
V = Voltage across the plates of the capacitor
Taking the first derivative, with respect to time, of both
sides of the capacitor equation, gives the following:
dq/dt = C dV/dt (C = Constant)
This gives the current (Charge vs. time) to charge a capacitor,
C, and dV/dt is the time rate of change of the voltage across
the capacitor as it charges.
dq/dt = I = C dV/dt,
or
dV/dt = I/C.
For MOS circuits, transistors switch when their gate voltage
exceeds the threshold voltage, Vt. Ramping up the voltage
from, let's say zero to Vt, will turn on the transistor. The
TIME it takes depends on dV/dt - the faster to switch (turn on)
the transistor,the faster dV/dt needs to be.
The Capacitance of an MOS transistor is determined by the oxide
thickness, length, and width of the transistor. It will have
its own inherent parasitic capacitance - gate overlap
capacitance (i.e., Miller capacitance) among others.
Now, imagine some circuit stage driving an MOS transistor
through a long metal conductor. The driving stage will source
some "fixed" amount of current, I.
Thus, the voltage rise across the MOS capacitor will be
determined, to a first order, by I/C.
Any additional parasitic capacitance, in PARALLEL with the MOS
transistor, will result in increased effective capacitance
(Capacitors in parallel have their capacitances ADD)
Now, parasitic capacitances due to one metal trace overlapping
another trace, or running parallel to a third trace (as in long
address & data buses) will increase the overall capacitive load
that the charging current has to drive, C.
dV/dt = I/C is therefore reduced as C is increased (for a fixed charging current, I), decreasing the rise time of the waveform trying to switch (i.e., turn on) the intended MOS transistor gate.
Back to PMAT
PMAT is describing a material that will reduce the stray
capacitances by lowering the dielectric constant of the
material surrounding the metal traces - i.e., it will LOWER C,
thereby increasing dV/dt and speeding up circuits.
Difficulties
I haven't seen any details of the technique, but the press
release described a process whereby a liquid form of glass is
applied to a wafer. This sounds like a "spin-on glass" procedure
with some form of carbon-doped glass . Note -the details were
less than specific.
In a way, this is quite surprising, since PMAT has been a
supplier of Plasma deposition and Etch equipment - all DRY
operations!
Now, spin-on-glass (SOG), if that is what the technique is, has
been around for a long time. It has been used for depositing
glass layers, doping source-drains (When the glass contains
arsenic), and as "planarization" technique.
In fact, many MOS processes adopted SOG in the early 1990s when
multi-layer metal processes became popular.
The SOG process, which requires multiple spin cycles, drying
cycles, and bake cycles to drive off organic volatiles, sort of
produced smooth, undulating topology over polysilicon and
metal layers, allowing subsequent metal layers to be deposited
fairly "flat". Flatness is required to facilitate photomasking
steps - that is, to print patterns on metal layers so that they
can then be etched into metal lines, connecting various circuit
elements together. If metal lines have to cover 3 dimensional topology, the metal films tend to have non uniform thickness between the peaks and valleys - making it a nightmare to etch - bridging between adjacent metal traces frequently occurs where the metal films are thick - as in the valleys of undulating surfaces.
However, SOG processes are tricky, variable, messy and
sub-optimal. The material tends to vary from lot to lot -
viscosity, solids contents, volatility. spinning the liquid on
the wafer, although relatively cheap and efficient, can result
in weird artifacts - bubbles in the film. "cat-eyes", etc.,
and subtle things such as relative humidity changes in the
fab/yellow room, etc. come into play.
Finally, after spinning and drying the films, the wafers have
to be baked at high temperature to drive all the volatile
organics - and this again can lead to artifacts in the "glass"
film - voids, cracks (especially at sharp, 90 degree corners
around wide metal traces), etc. Basically, there are many headaches that prevent SOG operations from becoming automated
and efficient.
More recently, CMP techniques have become very popular.,
Chemical-Mechanical-Planarization (CMP) is a series of
depositions of thick oxides (usually by CVD or Plasma CVD
techniques), followed by mechanical polishing that FLATTENS
the top surface of the deposited oxide.
Vias are etched in the oxide to connect to lower levels of
metallization, and the vias are filled with "plugs", most
often with tungsten and titanium contact/barrier metallization.
The CMP approach can reduce vertical parasitic capacitances by
increasing d, the separation between two metal layers, because
the deposited oxide films can be deposited quite thickly, then polished flat.
PMAT Future
All in all, reducing k, the dielectric constant, is an excellent
objective. However, IF (And I don't know about this) it requires
SOG processing, I'd say this will meet with limited acceptance.
The industry trend is to go to 4, 5 and 6 layers of metal using
CMP and related technologies.
If PMAT can deposit these films using a CVD reactor (TEOS with
carbon doping, for example) they might have a better shot at
going after the "current mainstream".
In summary - a promising concept, but a Long Shot in its current incarnation.
Paul |
