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Technology Stocks : Cyrix 1 Where anything goes

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To: FJB who wrote (176)	2/13/1997 5:57:00 PM
From: fuchi	of 640

More GX information to share Hi guys: Do you still remember the EE Times report "M2 architecture makes instructions count"? By Robert Maher, Vice President of Engineering, Cyrix Corp., Richardson, Texas In his report advising Intel designers how to design a better MMX2, Robert mentioned two new Cyrix's exclusive architecture features "lockable on-chip cache" and "scratch-pad RAM": Cyrix configured the M2's on-chip cache so that lines can be locked, a feature not included in the Intel implementation. That creates, in essence, a scratch-pad RAM capability and provides a deterministic access that boosts performance, given that the M2's pipeline architecture provides access to the stored values as fast as if the data were in a register. Code can also be executed deterministically for real-time data processing. This report is located at: techweb.com What interesting is that I found out from our friends in Cyrix that Cyrix Media GX also has these two advanced performance features to boost its system performance. These information is too good not to share with all of you. <-deleted-> The gx can lock up to 1 set (4k of the 16k cache) for critical smi(emulation code for vga and/or audio) code and scratchpad memory for the graphics controller. The controller can render graphics at the 120/133mhz core frequencies and dump the finished product into the video frame buffer in dram. Keep in mind that the performance of these graphics functions will scale linearly when you get to 150/166mhz and beyond. An external graphics controller will not get this kind of benefit as the microprocessor frequency scales. The m2 will have this same lockable cache feature. There is absolutely no need for an L2 cache on the gx. In fact it would slow down the processor. You cant do a real apples to apple comparison on memory timings between the gx and burst buses like the pentium and 486. The gx derives its timings from the internal core clock(ie 120/133mhz and has very fine granularity in adjusting its timings). A pentium or 486 bus memory controller is on the bus and the memory controller derives its timings off of the 66mhz clock. It has less granular timings. In addition there are delays due to the data path through the chipset. So when one talks about a 3-1-1-1 burst timing they are not taking into account how many clocks it took for the initial signal to come out of the pentium and the delay into the chipset.... This adds more clocks on the front end of the burst. The gx has none of these delays and with its more granular resolution on memory timings it can burst bits out of the pagemode or edo dram at a faster cycle time(say 25nsec instead of 40nsec on typical 60-70nsec drams). In addition the gx is not limited to a 4 word burst. When the display controller is pulling in a scan line it can pull many sequential 64bit words out of the dram as long as it is still addressing the same row inthe dram. This same analysis goes for looking at an l2 cache. There are the same kind of delays through the cache controller chip and it is fairly inefficient in getting data out and is limited to 4 32bit words(linesize in the pentium). <-deleted-> Thanks to our friends in Richardson and their contriubtions to build a better tomorrow for all of us. I hope that all of you enjoy it! You know that I love Cyrix's innovations! Fuchi ... who loves Cyrix's innovations

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