<Sorry Ali but you got things backwards. 'Sequential gates'? You mean combinational gates between sequential elements.>
If you do not understand what people mean when
they talk about digital logic, go learn something
first before barking, student.
The "number of sequential gates" means the number
of base logical elements (NORs, NANDs, XORs,
or whatever the basic library element is) across
whom a worst-case signal has to propagate
before the final logical state of the
particular logical function is achieved.
For an example that is comprehendable for you,
a simplest R-S-flip-flop may be
built using two 2-NAND gates. If it has a 1T delay
when flipping from 0 to 1 on direct output,
the inverted output will have 2T delay because
the signal has to propagate across TWO gates
to get through. There could be thousands of
these flip-flops in parallel, but the "gate depth"
is 2 in this case. More complex circuits like
decoders, comparators, shifters, multipliers
have apparently much more logic inside, so
some conditional or preset signals have to
propagate across several gates sequentionally.
There is a whole art of cuircuit synthesis
that is aimed to minimize this "sequentionality".
To understand the above topic up to the rights to
judge what is backward and what is straightforward,
your background should include at least the course
like this:
ece.wpi.edu
see Chapter 8.
Have a nice education, Elmer...
<end of the lecture>
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