Scumbria, >>>Race conditions usually can't be debugged by logic simulation, and require a
disciplined circuit design methodology to prevent their occurence.<<<
Races can be found by simulators, well in advance of any silicon. If back to back, or serial (one driving another) latches update on the same clock cycle, you have a race. Very simple. Of course, you have to have a simulator with very high coverage that looks at all these latch to latch combinations. This thing (OK at 300, 400, no good at 350 MHz seems to have come out of nowhere, so process may have shifted). The thing is, they should have enough margin in the design to allow for minor process shifts, and not get races out of nowhere. This sounds as mysterious as AMD's last "explanation", which was a "mask problem." This company is extremely shaky, to say the least, in design, or process, or simulation, or all of the above. I can't believe Gateway just signed up with them.
Tony |
