Scumbria and Tony,
Thank you both for your responses/discussion of this issue from the engineering perspective.
I think that I am hearing that AMD is perhaps not using a "disciplined circuit design methodology" to prevent/solve this problem. It is surprising that, if the problem is similar to the one they have been encountering for some time, they have not figured this out.
Is the "delay chain in one of the paths" merely a quick work-around, or is AMD eventually going to either re-engineer the aspect of the production process that is causing the glitch? Is AMD yet using the deeper pipelines to which you refer, Scumbria? And are AMD's circuit designers using the asynchronous dynamic logic chains or not (you say that designers frequently do, but not that AMD's do exclusively, are there other issues wrt this)? I wonder what Intel's solution(s) to these issues were.
Despite AMD's woes, it is unfathomable that they would not have the potential to solve these problems. Could it be that in the rush to ramp-up corners were cut? If so, it would seem that Intel's market moves are pressuring not just AMD's pricing, but also their process.
I appreciate this discussion, although it is somewhat over my head, I am pleased to peer into the belly of this beast.
Chris |
