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Politics : Formerly About Advanced Micro Devices
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To: Tony Viola who wrote (53191)3/22/1999 4:19:00 PM
From: Scumbria  Read Replies (2) of 1583146
 
Tony,

Why is it better to get results out of the cache in three cycles, rather than in two cycles?

It has been demonstrated in design after design that the per-cycle performance benefit of a shorter pipeline is far outweighed by the clock speed penalty inherent in a short pipeline.

Early in the decade processor architects split into two camps- "screamers and super-brainers" Alpha was a "screamer" and PPC, M1, K6, P6 went the way of the "super-brainers". The PPC 604 executed a lot of instructions per clock, but ran at a very low clock speed. In contrast, the Alpha 21064 executed fewer instructions per clock but ran at a much higher clock speed.

The "super-brainers" have emerged from this battle battered and bruised, and now everyone is using the Alpha approach. This is evidenced by the microarchitecture of K7, Willamette, and M3. (I'm not sure that IBM has caught on yet.)

Scumbria
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