Scumbria,
I understand what you mean about cramming a lot of logic between clock cycles, vs. running a chip at a higher clock speed with less logic per cycle, and the tradeoffs between the two philosophies. OK, but if you go too far with the latter, the overhead, or lost time in each clock cycle for setup time of latches, can result in the law of diminishing returns taking over. Assuming an all synchronous design, before every clock strikes, you have to ensure all switching has settled, or long path failures occur. To the extreme, if you allowed, e.g., only one combinatorial level between clocks (wouldn't get much done), setup time would become a large part of the cycle, and all of it is wasted. This isn't done, of course, but it's just to emphasize that going too fast is wasteful also.
Not easy to express the above in words. A picture or a whiteboard and marker would be much better.
Still, I don't get how, given two designs that have reasonably close clock speeds, the one with a three cycle cache access is better than one with two. 'Splain?
Tony |
