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Politics : Formerly About Advanced Micro Devices
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To: Yousef who wrote (54038)4/3/1999 2:45:00 PM
From: Shane Geary  Read Replies (3) of 1570831
 
Re: "Physical separation is an obvious and easy thing to do as one approach. BTW, there is a considerable amount of copper in your Fab right now. the aluminum used as interconnect contains .5% Copper for example."

Yousef,

I fall somewhat between the two stools occupied by yourself and Process Boy. First of all, the 0.5% copper in AlCu and AlSiCu hangs around the Al grain boundaries and doesn't move. Cu precipitates can be created during metal etch since Cu does not volatalize easily (this is why it is kept to ~0.5%, and why Cu interconnect is polished off rather than etched off in Cu interconnect schemes). This leads to corrosion issues. However, the Cu in the AlCu does not affect transistor reliability.

Only when pure Cu is used does the problem of Cu diffusing through SiO2 to the silicon surface arise. The first risk is that the integrity of the underlying barrier metal fails and the second risk, as PB mentions, is that of contamination of other process steps.

I don't think that this should affect the decision as to WHEN to go to Cu. These problems will have to be faced whenever that is done and Intel will face them in the generation after 0.18um.

I agree that it is the process integration issues (to me: barrier/seed layer integrity and Cu CMP) that are the worries.

By the way, well implemented dual-damascene Cu inteconnect can reduce costs, that may an advantage in using it.

As to whether it speeds up chips or not - answer the question of whether the chip is gate delay-limited or interconnect RC delay-limited. Not easy to do - look at the difficulties the software models have. Perhaps the best answer is " Don't need Cu at 0.25um, need Cu at 0.15/0.153um, some benefit at 0.18um"?
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