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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (54365)4/5/1999 10:26:00 PM
From: Tenchusatsu  Read Replies (1) of 1578096
 
From the link you posted:

A multicycle data cache extends the load-use penalty, that is, the number of cycles an instruction must wait if it requires data from an immediately preceding load instruction. This delay would sap the performance of an in-order processor, but an out-of-order processor simply executes nondependent instructions while waiting for the data cache.

As if it were this simple. If non-dependent instructions were abundant, then yes, the delay would have no effect. But this is x86 code we're talking about, not the clean RISC instruction set of the Alpha. Even Microprocessor Report thinks that the 3-IPC limit will rarely be hit, meaning that there aren't that many non-dependent instructions to execute in the first place.

People here were all excited that the K7 will resemble technology from Digital's Alpha. Well, it seems that this is one piece of evidence which shows that what worked for the Alpha won't necessarily work for the x86 architecture.

Tenchusatsu
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