Paul - Cu processing detail
< You are ignoring SIGNIFICANT DETAILS.>
Yes I did, from the stand point of debating the technology. The response I posted that you are reffering to I was simply posting the the cursory theory of what the potential Cu benefit is. That is all it was meant to be, for informational purposes only. I am still of the belief that Intel's approach (Al for .18) is preferable, mainly due to the immaturity of the Cu process. To make Cu work, and not contaminate the fab, there certainly are costly measures that need to be taken.
Copper metallization lines in damascene processes need to be ENCAPSULTED by a thin film of barrier material to prevent diffusion into the surrounding oxides and silicon substrate.
With metallization linewidths approaching .25 to .35 microns, the 0.030 to 0.050 micron barrier film thicknesses ENCROACH ON BOTH SIDES of the copper, REDUCING the copper cross sectional area, thereby increasing the resistance of the copper traces. For example, a 0.03 barrier film will reduce a 0.25 micron damascene "trench" to 0.19 microns wide for the copper to then fill.
Yep. And the barrier material has much greater resistivity than Cu, or even Aluminum. I don't have any detail on what the MOT process uses for it's "Barrier/Seed" layer. I know what Intel uses on it's .13 line, and it's pretty exotic. (Sorry, can't tell you). The game is to get the Barrier layer as thin as possible without allowing the Cu to diffuse through the dilectric to the transistors as the wafers are thermally cycled through during the manufacturing process. The thicker the barrier layer, the better the protection against Cu diffusing. However, the inherent benefit of the Cu is diminished, as the cross sectional area of the Cu is diminished, as you have described.
Tradeoffs abound with this technology.
Paul
One other tradeoff I can think of is the Dielectric process, from the standpoint that the dielectric layer processes needed with Cu are also extremely immature!!! The materials are exotic and difficult to work with. In contrast, for .18 Intel just added some F to standard SiO dielectric to realize some gain in RC effects. This is not terribly exotic and can use the same equipment set as previous generation technology.
PB
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