SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (54368)4/5/1999 11:07:00 PM
From: Scumbria  Read Replies (2) of 1577799
 
Ten,

x86 data dependencies actually decrease the penalty of a multi-cycle cache. If instruction 2 is stalled waiting for data from instruction 1, it gives instruction 3 extra time to do a cache lookup without performance penalty. I don't think your argument works.

Multicycle caches have an impact if every instruction is relying on data from the cache, and bubbles form in the pipeline due to branch misprediction.

K7 is going to have excellent performance for synthetic benchmarks like SPECint, though I doubt it will run Winstone any faster than anybody else.

Scumbria
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext