Paul - Article about Cu / Low K dielectric process development
From 8/98, but not much has changed since then. PB.
news.semiconductoronline.com
Sematech Accelerates Copper and Low-k Transitions 08/10/1998
Copper wiring and low-k dielectrics reduce circuit delays and noise, eliminating interconnect layers. Still, many questions about process compatibility and integration must be answered before these new materials can be implemented in large scale production. According to Paul Winebarger, recently appointed director of interconnects at Sematech (Austin, TX), the consortium seeks to help member companies determine which approaches are viable. Within the next three years, Winebarger hopes to accelerate Sematech's work on advanced interconnects, pushing dielectric constants (k) down to 1.5 (SiO2 has a k value of about 4, the value for air is 1) and achieving copper fill of 100 nm (0.1 micron) features.
Below a dielectric constant of 2.5 or so, there is no industry consensus on which materials will work best (See related article). Winebarger expects Sematech to make a significant contribution to low-k materials characterization. Any candidate material will need to minimize high frequency signal loss, as the Semiconductor Industry Association (SIA; San Jose, CA) roadmap puts high performance clock speeds at 1.4 GHz by 2001. Meanwhile, the high numerical aperture optics needed to print 100-nm features have very narrow depth-of-focus. Chemical mechanical planarization (CMP) will be used to flatten wafer topography and improve focus (See related article), so candidate low-k materials must be able to withstand the mechanical stress of the polishing process.
Optimizing low-k processes is especially difficult because the candidate materials all have different chemistries and properties. Some steps, like etch, may require a different process chemistry and recipe for each material, Winebarger told Semiconductor Online. Others, like spin coating with good step coverage, are more likely to be transferable.
As copper and low-k materials begin to appear in the same chips, compatibility will become more important and integration issues will become more complex. Copper diffusion barrier adhesion and effectiveness, already critical issues with SiO2 dielectrics, will be the key to low-k integration.
Aluminum damascene wiring appeals to some companies because it simplifies the process without the radical changes required by copper (See related article). Winebarger expects most Sematech members to switch directly to copper, however. For any particular company the choice will depend on product mix: delay-limited chips will realize a greater benefit from copper wiring than transistor-limited chips. Aluminum damascene is not without integration issues, either. For example, Al tends to scratch and smear easily during CMP.
Winebarger, who will remain a Motorola employee while on assignment at Sematech, is currently MOS-11 Photo/Etch Process Engineering Manager for Motorola in Austin. He is responsible for all process development associated with photo and etch areas of the 200 mm high volume wafer fab.
By Katherine Derbyshire
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