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Politics : Formerly About Advanced Micro Devices
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To: Steve Porter who wrote (55812)4/18/1999 2:36:00 PM
From: Jim McMannis  Read Replies (1) of 1578922
 
Steve from what I understand the K7 was reported in the tests as 3k cache and 64 cycle latency. This should have been 64k L1 cache with a 3 latency. That could have been a grammatical error. EXCEPT that the K7 will have 128K L1 cache. So anyway you look at it the test was flawed.
Besides that we still don't know if the Coppermine will have a 32k L1 cache or 64k.
Kind of hard to believe a Stanford class could switch the cache size with the latency cycles.

Jim
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