Here is some basic information from patent 5,602,987. Definitely a patent with broad claims concerning disk emulation. Claims 10, 17 and 35 are very broad and concern the general concept of emulating a disk drive with an array of EEPROM cells. Claims 1 and 23 include redundancy features. I don't know which claim or claims are at issue in the suit, but I can assure you that this technology is now widely used and there must be many companies watching this suit very carefully. I haven't heard of any prior art becoming known to make these claims invalid. The original filing date is in April 1989!
DIALOG(R)File 340:CLAIMS(R)/US Patent
(c) 1999 IFI/Plenum Data Corp. All rts. reserv.
2813175 3709639
E/ FLASH EEPROM SYSTEM
Document Type: UTILITY
Inventors: Harari Eliyahou (US); Mehrotra Sanjay (US); Norman Robert D (US)
Name and Address of Inventors: Harari, Eliyahou, Los Gatos, CA, (US);
Mehrotra, Sanjay, Milpitas, CA, (US); Norman, Robert D, San Jose, CA,
(US)
Assignee: SanDisk Corp Assignee Code: 39207
Name and Address of Assignee: SanDisk Corporation, Sunnyvale, CA
Primary Examiner: Beausoliel, Jr, Robert W
Assistant Examiner: Hua, Ly V
Attorney, Agent or Firm: Majestic, Parsons, Siebert & Hsue
Patent Issue Applic Applic
Number Date Number Date
------------ -------- ------------- --------
Patent: US 5602987 19970211 US 93174768 19931229
(Cited in 001 later patents)
Continuation of: US 5297148 US 92963838 19921020
Division of: ABANDONED US 89337566 19890413
Priority Applic: US 93174768 19931229
US 92963838 19921020
US 89337566 19890413
Calculated Expiration: 20140211
Abstract:
A system of Flash EEprom memory chips with controlling circuits serves as
non-volatile memory such as that provided by magnetic disk drives.
Improvements include selective multiple sector erase, in which any
combinations of Flash sectors may be erased together. Selective sectors
among the selected combination may also be de-selected during the erase
operation. Another improvement is the ability to remap and replace
defective cells with substitute cells. The remapping is performed
automatically as soon as a defective cell is detected. When the number of
defects in a Flash sector becomes large, the whole sector is remapped. Yet
another improvement is the use of a write cache to reduce the number of
writes to the Flash EEprom memory, thereby minimizing the stress to the
device from undergoing too many write/erase cycling.
Number of Claims: 050
Exemplary Claim:
D R A W I N G
1. A method of operating a computer system including a processor and a
memory system, wherein the memory system includes an array of
non-volatile floating gate memory cells partitioned into a plurality of
sectors that individually include a distinct group of said array of
memory cells that are erasable together as a unit, comprising: providing
said memory array and a memory controller within a card that is
removably connectable to the computer system, said controller being
connectable to said processor for controlling operation of the array
when the card is connected to the computer system, partitioning the
memory cells within the individual sectors into at least a user data
portion and an overhead portion, detecting a predefined condition when
individual sectors become unusable and linking the addresses of such
unusable sectors with addresses of other sectors that are useable,
causing the controller, in response to receipt from the processor of an
address in a format designating at least one magnetic disk sector, to
generate an address of a non-volatile memory sector that corresponds to
said at least one magnetic disk sector, accessing a usable sector of the
memory system, if the sector with the generated address is unusable, by
referring to the linked address of another sector that is usable and
then accessing that other sector, either writing data to, or reading
data from, the user data portion of the accessed usable sector, and
either writing to, or reading from, said overhead portion of the
accessed usable sector, information related to either the accessed
usable sector or data stored in the user data portion of said accessed
useful sector.
Non-exemplary Claims:
2. The method according to claim 1, wherein the detecting of the predefined
condition includes detecting when individual sectors become defective.
3. The method according to claim 2, wherein the detecting of when
individual sectors become defective includes determining when a number
of individual defective memory cells within a sector exceed a given
number.
4. The method according to claim 1, wherein the user data portion of the
individual non-volatile memory sectors has a capacity of substantially
512 bytes.
5. The method according to claim 1, wherein the information stored in the
overhead portion of the individual sectors includes an address of the
respective ones of the individual sectors.
6. The method according to claim 1, wherein the information stored in the
overhead portion of the individual sectors includes an error correction
code calculated from data stored in the user data portions of
corresponding ones of the individual sectors.
7. The method according to claim 1 wherein linking the address of unusable
sectors with sectors that are useable includes maintaining a list within
the card that links such unusable sectors with addresses of
corresponding ones of the other sectors that are useable, and wherein
accessing a usable sector includes referring to the list to translate
the address of the unusable sector into an address of a usable sector.
8. The method according to claim 1 wherein linking the address of such
unusable sectors includes storing within individual ones of the
defective sectors addresses of corresponding useable sectors, and
wherein accessing a usable sector corresponding to an unusable sector
includes referring to the useable sector address stored in the unusable
sector.
9. The method according to claim 1, wherein causing the controller to
generate an address of a non-volatile memory sector includes doing so
for a non-volatile memory sector that corresponds to only one magnetic
disk sector, wherein the user data portion of the individual
non-volatile memory sectors has a capacity that is substantially the
same as a user data portion of said one magnetic disk sector.
10. A method of operating a computer system including a processor and a
memory system, wherein the memory system includes an array of
non-volatile floating gate memory cells partitioned into a plurality of
sectors that individually include a distinct group of said array of
memory cells that are erasable together as a unit, comprising: providing
said memory array and a memory controller within a card that is
removably connectable to the computer system, said controller being
connectable to said processor for controlling operation of the array
when the card is connected to the computer system, partitioning the
memory cells within the individual sectors into at least a user data
portion and an overhead portion, causing the controller, in response to
receipt from the processor of an address in a format designating at
least one magnetic disk sector, to designate an address of at least one
non-volatile memory sector that corresponds with said at least one
magnetic disk sector, either writing user data to, or reading user data
from, the user data portion of said at least one non-volatile memory
sector, and either writing to, or reading from, said overhead portion of
said at least one non-volatile memory sector, overhead data related
either to said at least one non-volatile memory sector or to data stored
in the user data portion of said at least one non-volatile memory
sector.
11. The method of claim 10, wherein the user data portion of the individual
sectors has a capacity of substantially 512 bytes.
12. The method of claim 10, wherein the overhead data stored in said
overhead portion of the individual sectors includes addresses of the
individual sectors.
13. The method of claim 10, wherein partitioning the memory cells includes
partitioning said memory cells within the individual sectors to include
an additional portion of spare memory cells.
14. The method of claim 13, wherein the overhead data stored in said
overhead portion of the individual sectors includes an identification of
any defective cells within the user data portion of corresponding ones
of said sectors, said method additionally comprising causing the
controller to read the identification of defective cells from the
overhead portion of said addressed at least one non-volatile memory
sector and then to substitute therefore other cells within the spare
cell portion of the addressed at least one non-volatile memory sector.
15. The method of claim 10, additionally comprising causing the controller
to identify and store addresses of any defective non-volatile memory
sectors within the array, and, wherein designating an address of a
sector includes, in response to designating an address of a defective
sector, substituting an address of another sector instead.
16. The method of claim 10, wherein the individual sectors include only one
user data portion and only one overhead data portion.
17. A memory system on a card that is connectable to a host computer
system, said memory system comprising: an array of non-volatile floating
gate memory cells partitioned into a plurality of sectors that
individually include a distinct group of said memory cells that are
erasable together as a unit, the individual sectors having enough cells
for storing a given amount of user data and overhead data, and means
connectable to said computer system for controlling operation of the
array, said controlling means including: means responsive to receipt of
a magnetic disk sector address from the host computer system for
addressing a corresponding non-volatile memory sector, means for reading
the overhead data stored in the addressed sector prior to either reading
the user data from, or writing user data to, the addressed sector, and
means responsive to the read overhead data for executing an instruction
from the host computer system to perform a designated one of reading
user data from, or writing user data to, the addressed sector.
18. The memory system according to claim 17 wherein said controlling means
additionally includes means listing any unusable ones of said plurality
of non-volatile memory sectors for linking said unusable sectors with
others of said sectors that are usable, and wherein said non-volatile
memory sector addressing means includes means for accessing linked
others of said sectors in place of said unusable sectors.
19. The memory system according to claim 17 wherein said given amount of
user data is substantially 512 bytes.
20. The memory system according to claim 17 wherein said magnetic disk
sector address includes a head, cylinder and sector.
21. The memory system according to claim 17 wherein the individual sectors
of the memory array additionally have enough cells for providing
redundant cells in excess of that necessary to store said given amount
of user data and said overhead data, said controlling means additionally
including means for substituting redundant cells of a sector for any
defective cells within the sector.
22. The memory system according to claim 21 wherein said substituting means
including means referencing the overhead data of an addressed sector for
substituting redundant cells within the addressed sector.
23. A memory system having electrical terminations for establishing a
connection with a host computer system, said memory system comprising:
an array of non-volatile floating gate memory cells partitioned into a
plurality of sectors that individually include a distinct group of said
memory cells that are erasable together as a unit, the individual
sectors having enough cells for storing a given amount of user data and
some overhead data, and a memory controller connected between said
electrical terminations and said memory cell array for controlling
operation of the array, said controller including: means responsive to
receipt of one or more mass memory storage block addresses through said
terminations for addressing one or more of the non-volatile memory
sectors, said addressing means including means responsive to an
identification of any of the non-volatile memory sectors that are
unusable for substituting another usable sector therefor, means for
reading overhead data stored in the addressed sector prior to either
reading the user data from, or writing User data to, the addressed
sector, and means responsive to the read overhead data for either
reading user data from, or writing user data to, the addressed sector.
24. The memory system according to claim 23 wherein the identification of
any unusable sectors includes a list maintained within the memory system
unit that links addresses of unusable sectors with corresponding usable
sectors.
25. The memory system according to claim 23 wherein the identification of
any unusable sectors includes a record of individual addresses of
substitute usable sectors stored as part of the overhead data in
respective ones of the unusable sectors.
26. The memory system according to any one of claims 23-25 wherein the
identification of any unusable sectors includes inoperable or defective
sectors.
27. The memory system according to any one of claims 23-25 wherein the
identification of any unusable sectors includes sectors that contain a
number of defective cells in excess of a preset number.
28. The memory system according to any one of claims 23-25 wherein said
given amount of user data is substantially equal to 512 bytes.
29. The memory system according to any one of claims 23-25 wherein said
controller additionally includes means for selecting a plurality of
sectors for an erase operation, and means for simultaneously performing
an erase operation on only the selected plurality of sectors.
30. The memory system according to claim 23 wherein said individual
non-volatile memory sectors additionally have redundant memory cells in
excess of that necessary to store said given amount of user data and
said overhead data, said controller additionally including means for
substituting redundant memory cells of an individual sector for
defective memory cells within the individual sector.
31. The memory system according to claim 23 wherein the overhead data
reading means includes means for reading from the overhead data of an
addressed sector an address of that sector, and wherein the controller
additionally includes means for comparing the read overhead data address
with the address of the sector, thereby to confirm that the desired
sector has been addressed.
32. The memory system according to any one of claims 23-25, 30 and 31
wherein the given amount of user data that is storable in individual
sectors is substantially equal to a size of individual mass memory
storage blocks of the host computer system, and wherein the addressing
means maps addresses of individual ones of the mass memory storage
blocks into unique individual ones of the non-volatile memory sectors.
33. The memory system according to any one of claims 23-25, 30 and 31
wherein said memory system unit is implemented on a single printed
circuit card.
34. The memory system according to any one of claims 23-25, 30 and 31
wherein the one or more mass memory storage block addresses to which the
controller addressing means is responsive consists of one or more
magnetic disk sector addresses.
35. In a computer system including a processor and a memory system, wherein
the memory system includes an array of integrated electronic circuit
non-volatile floating gate memory cells partitioned into a plurality of
distinct sectors of said memory cells that are individually erasable
together as a unit separately from other sectors, a method of operating
the memory system, comprising: removably connecting said memory system
including a controller to the computer system in a manner that said
controller communicates with said processor for controlling operation of
the array, in response to receipt from the processor of an address in a
format designating at least one mass memory storage block, generating
through the controller (1) an address of at least one of said plurality
of sectors of non-volatile memory corresponding to said at least one
mass memory storage block and (2) an erase, write or read command, in
response to an erase command, erasing said at least one sector, in
response to a write command, reading, from an overhead portion of said
at least one sector, overhead data of a characteristic of said at least
one sector, and thereafter writing user data in the user data portion of
said at least one sector and writing a characteristic of the written
user data in the overhead portion of said at least one sector, and in
response to a read command, reading, from an overhead portion of said at
least one sector, overhead data of a characteristic of said at least one
sector or of data stored in the user data portion of said at least one
sector, and thereafter reading data from the user data portion of said
at least one sector.
36. The method of claim 35, which additionally comprises storing within the
memory system links from addresses of any unusable sectors to addresses
of others of said plurality of sectors, and wherein generating an
address of said at least one of said plurality of sectors includes
referring to said address links to substitute an address of a useable
sector for an address of an unusable sector.
37. The method of claim 36 the address links are stored for sectors that
are unusable by reason of more that a predetermined number of memory
cells therein being defective.
38. The method of claim 36 wherein any links to addresses of useable ones
of said plurality of sectors are stored in the overhead portion of
unusable ones of said plurality of sectors.
39. The method of claim 35 wherein erasing said at least one sector
includes simultaneously erasing two or more but less than all of said
plurality of sectors.
40. The method of claim 36 wherein generating an address of said at least
one sector includes generating addresses of a number of said plurality
of sectors that is equal to a number of mass memory storage block
addresses received from the processor.
41. The method of claim 40, wherein the user data portion of the individual
sectors has a capacity of substantially 512 bytes.
42. The method of claim 35, wherein the overhead data stored in said
overhead data portion of said at least one sector includes the address
of said at least one sector.
43. The method of claim 42, wherein, in response to either the write
command or the read command, overhead data that is read includes the
address of said at least one sector.
44. The method of claim 43, wherein the address read from the overhead
portion of said at least one sector is compared with the address that
was generated through the controller.
45. The method of claim 35, wherein the overhead data stored in said
overhead data portion of said at least one sector includes, if said at
least one sector is defective, an address linking said at least one
sector to another of said plurality of sectors.
46. The method of claim 45, wherein generating an address of said at least
one of said plurality of sectors includes referring to said address
linking to substitute an address of a useable sector for an address of
an unusable sector.
47. The method of claim 35, wherein the overhead data stored in said
overhead portion of said at least one sector includes an identification
of any defective cells within the user data portion of said at least one
sector.
48. The method of claim 47, additionally comprising, in response to either
the write command or the read command, reading through the controller
the identification of defective cells from the overhead portion of said
at least one sector and then substituting therefore other cells within
the said at least one sector.
49. The method of claim 35, wherein the writing of a characteristic of the
user data includes calculating an error correction code from the written
user data and writing said error correction code into the overhead
portion of said at least one sector.
50. The method of claim 35, wherein said at least one mass memory storage
block sector address received from the processor includes a head,
cylinder and sector.
Class: 395182060
Class Cross Ref: 365200000; 365210000; 711100000
IPC: G06F-011/00
Field of Search: 365185090; 365189070; 365200000; 365201000; 371010200;
371010300; 371040100; 395182030; 395182040; 395182050; 395182060;
395427000; 395430000; 395575000
Art Unit: 243
U.S. References Cited:
Patent Date
Number YYYYMM Class Inventor
---------- ------ ------------ ----------
US 3633175 197201 395435000 Harper
US 4051354 197709 365200000 Choate
US 4093985 197806 395185020 Das
US 4210959 198007 395894000 Wozniak
US 4250570 198102 365200000 Tsang et al.
US 4279024 198107 365185220 Schrenk
US 4281398 198107 365200000 McKenny et al.
US 4295205 198110 395410000 Kunstadt
US 4354253 198210 395182060 Naden
US 4355376 198210 365200000 Gould
US 4380066 198304 371010200 Spencer et al.
US 4405952 198309 360049000 Slakmon
US 4422161 198312 365185090 Kressel et al.
US 4450559 198405 395182040 Bond et al.
US 4456971 198406 395500000 Fukuda et al.
US 4463450 198407 371010100 Haeusele
US 4479214 198410 371002200 Ryan
US 4493075 198501 365200000 Anderson et al.
US 4498146 198502 395442000 Martinez
US 4514830 198504 365185090 Hagiwara et al.
US 4525839 198506 371038100 Nozawa et al.
US 4527251 198507 395182060 Nibby, Jr. et al.
US 4601031 198607 371030000X Walker et al.
US 4612640 198609 371040100 Mehrotra et al.
US 4616311 198610 395416000 Sato
US 4617624 198610 395402000 Goodman
US 4617651 198610 365200000 Ip et al.
US 4642759 198702 395500000 Foster
US 4654847 198703 395182040 Dutton
US 4672240 198706 326107000 Smith et al.
US 4688219 198708 365200000 Takemae
US 4718041 198801 365185220 Baglee et al.
US 4733394 198803 365200000 Giebel
US 4746998 198805 360072100 Robinson et al.
US 4757474 198807 365189070 Fukushi et al.
US 4774700 198809 369054000 Satoh et al.
US 4785425 198811 365052000 Lavelle
US 4794568 198812 365185090 Lim et al.
US 4796233 198901 365200000 Awaya et al.
US 4800520 198901 235382000 Iijima
US 4887234 198912 395497040 Iijima
US 4896262 199001 395500000 Wayama et al.
US 4914529 199004 360048000 Bonke
US 4920518 199004 365228000 Nakamura et al.
US 4924331 199005 360072100 Robinson et al.
US 4942556 199007 365200000 Sasaki et al.
US 4945535 199007 Hosotani et al.
US 4949240 199008 395600000 Iijima
US 4949309 199008 365185120 Rao
US 4953122 199008 395404000 Williams
US 5043940 199108 365185030 Harari
US 5053990 199110 395430000 Kreifels et al.
US 5070474 199112 395416000 Tuma et al.
US 5095344 199203 365185030X Harari
US 5226168 199307 395800000 Kobayashi et al.
US 5297148 199403 365200000 Harari et al.
Foreign References Cited:
Patent Date
Number YYYYMM Class
---------- ------ ------------
AU 557723 198701
EP 220718 198705
EP 243503 198711
EP 300264 198901
EP 86886 198308
GB 2136992 198409
JP 1054543 198903
JP 58215794 198312
JP 58215795 198312
JP 59162695 198409
JP 5945695 198403
JP 60076097 198504
JP 60212900 198510
JP 60178564 198602
JP 6196598 198605
JP 62283496 198712
JP 62283497 198712
JP 63183700 198807
WO WO8400628 198402
Other References Cited:
Advanced Data Sheet, ''48F010 1024K Flash EEPROM,'' SEEQ Technology,
Incorporated, pp. 2-13 thru 2-24 (Oct. 1988).
Clewitt, ''Bubble Memories as a Floppy Disk Replacement,'' 1978 Midcon
Technical Papers, vol. 2, pp. 1-7, Dec. 1978.
Data Sheet: ''27F256 256K(32K X 8) CMOS Flash Memory,'' Intel Corporation,
pp. 1-24 (May 1988).
Hancock, ''Architecting a CCD Replacement for the IBM 2305 Fixed Head Disk
Drive,'' Eighteenth IEEE Computer Society International Conference, pp.
182-184, 1979.
Lai, Robert S., Writing MS-DOS Device Drivers, The Waite Group, Inc., Sep.
1987, pp. i-xi and 235-319.
Lucero et al., ''A 16 kbit Smart 5 V-only EEPROM with Redundancy,'' IEEE
Journal of Solid-State Circuits, vol. SC-18, No. 5, pp. 539-543 (Oct.
1983).
Miller, ''Semidisk Disk Emulator,'' Interface Age, p. 102, Nov., 1982.
Preliminary Data Sheet, ''48F512 512K Flash EEPROM,'' SEEQ Technology,
Incorporated, pp. 2-1 thru 2-12 (Oct. 1988).
Torelli et al., ''An Improved method for programming a word-eras-able
EEPRPOM,'' Alta Frequenza, vol. 52, No. 6, pp. 487-494 (Nov.-Dec.
1983).
Wilson, ''1-Mbit flash memories seek their role in system design,''
Computer Design, vol. 28, No. 5, pp. 30-32, (Mar. 1989).
Number of Figures in Patent: 10
Number of Drawing Sheets Issued: 5 |
