SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYRIX / NSM
NSM 18.270.0%Jul 31 5:00 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: kash johal who wrote (31528)4/20/1999 10:41:00 PM
From: Dan B.  Read Replies (3) of 33344
 
kash,

Re: "Gee Darren, the ramp up has been so phenomenal that we may have missed the
parts altogether.

Or do you think all those 0.18 parts are being aged someplace for some special
purpose."

The trouble with this is obvious. The 10/98 news release clearly says 4th Q '99 release expected for 600-800mhz Jalapeno. Your post clearly seems based in some sort of reality you've invented out of whole cloth.

Pauls comment that Jalapeno "cleary doesn't work" since it isn't out yet, is therefore CLEARLY as ludicrous as your comment here. Perhaps the time for such statements as these will come...yet you have no legs to stand on to date with statements based wholly outside the truth of NSM's stated approximate timeframe here. Living in the past is not NSM's stated intention. Past performance does not guarantee future similar performance.

Have patience kash, your foot is irrevocably in your mouth already, even if NSM/Cyrix fails to ever bring out the Jalapeno- not a likely eventuality, IMHO.

Then too....

>>"We designed Jalapeno to deliver the highest performance engine for the
mainstream PC market," said Stan Swearingen, vice president of
marketing for Cyrix. "We found that the most significant bottlenecks in
system performance result from memory latency. Since our goal was to
optimize overall system performance, we focused our attention on
minimizing memory latency and maximizing bandwidth by implementing
an innovative on-chip caching scheme and memory controller. The high
level of integration minimizes die size, which means we can manufacture
at low cost and provide the best value in a high-performance processor."

Design Objectives
Jalapeno was designed with four main objectives in mind:

Operate at high clock speeds
Reduce memory latency and bottlenecks
Improve floating-point and 3D graphics performance
Minimize die size to deliver an integrated, low-cost solution

Jalapeno's deep pipeline and on-chip L2 cache are designed to overcome
bottlenecks typically associated with high-speed processors. By using an
11-stage pipeline, the design provides for scalability to beyond one
gigahertz clock speeds.
...An on-chip memory
controller, another feature of the design, provides a dramatic improvement
in memory bandwidth, allowing for a 3.2 GB per second transfer rate.

...Jalapeno also incorporates consumer-quality DVD playback capabilities
based on technology developed by National's Mediamatics subsidiary.<<

cyrix.com

This product may well do very well if it doesn't come out 'til 4th Q 2000!

If it comes out within a few months...well..., we'll see.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext