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Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 88.13+1.0%Nov 21 9:30 AM EST
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To: bundashus who wrote (19486)4/29/1999 2:07:00 AM
From: Alan Bell  Read Replies (3) of 93625
 
I also went through the paper and didn't find much of it directly applicable. It makes a number of assumptions that do not permit an apples to apples comparison - the use of 128 bit memory bus, the use of a limited set of instruction traces, certain ratios of processor to cache speed, using only 16 bit wide memory width for rdram, not including DDR, etc.

Given these tenuous assumptions, they seem to claim that the choice memory architecture is not very important for the current generation of systems but will become important for future generations as the difference in speed between the processor and memory increases.

At that point memory bandwidth starts becoming very important. Of course, this is a DRDRAM strong point. Also they claim that having many open rows is important, also a DRDRAM strong point.

Their analysis does not take into account performance enhancements due to possible architectural improvements. They mention the Alpha 21364 has a Rambus channel directly attached to the processor, thereby eliminating the chipset(memory controller) latency from the equation. (I wonder if Merced/MacKinley might use this technique.)

They also hint that future memory architecture may need to use more subtle techniques like victim caches, set associative row buffers. Of course, the combination of Intel and Rambus is uniquely positioned to develop new processor/memory architectural combinations. Intel has the simulation tools and processor expertise; Rambus has the DRam research capability and the business relationships with the fabs.

-- Alan

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