SLDRAM consortium recharters to focus on DDR-2 spec
A service of Semiconductor Business News, CMP Media Inc.
Story posted 3 p.m. EST/noon, PST, 4/28/99
By Jack Robertson
WASHINGTON -- The former SLDRAM Consortium is rechartering itself as Advanced Memory International to develop the chip
infrastructure behind the projected Double Data Rate-2 SDRAM, sources said today.
As previously reported, a JEDEC (Joint Electron Device Engineering Council) working group is drafting an industry standard for DDR-2,
expected to be completed by June. However, advanced DRAM specifications require a large supporting infrastructure -- including chip
sets, socket interfaces, testing programs, clocks, and motherboard specs -- to make the chip a reality.
Sources said the SLDRAM Consortium, which had atrophied when the rival wideband memory concept was overtaken by Direct Rambus
DRAM, reconstituted itself to develop the DDR-2 infrastructure.
Some of the I/O design of the old SLDRAM chip has been incorporated in the upcoming DDR-2 specification. Also, DDR-2 will be an
open industry advanced DRAM standard -- the goal of the original SLDRAM program in opposition to the proprietary Direct RDRAM
specification of Rambus Inc.
A spokesman for Advanced Memory International declined to comment on the report, but said an announcement will be made Friday about
the new organization.
Advanced Memory International will be chaired by Desmond Rhoden, of VLSI Technology Inc.'s chip-set division. Sources said the group
felt that a chip executive from non-memory company should direct the new group in order to avoid conflicts with Rambus Inc., which has
licensed virtually all DRAM firms to make Direct RDRAM as well.
The former SLDRAM Consortium was headed by Farhad Tabrizi, director of strategic marketing for Hyundai Electronics America Inc. in
San Jose.
In addition to VLSI Technology, members of Advanced Memory International include such former SLDRAM partners as Micron
Technology, Infineon Technologies (formerly Siemens Semiconductor), Hyundai Electronics, Fujitsu, Hitachi, Mitsubishi Electric, and
others.
The DDR-2 timetable calls for the JEDEC specification to go for ballot in June, with expected adoption by the end of the year. DRAM
makers are expected to start working on designs later this year with first silicon ready sometime in 2000. DDR-2 is slated to have data
rates of 3.2- to 4.8-gigabits per second -- 50%-to-double the data rate of the first DDR chips coming on the market in the second half of
1999.
Although using a new design, the DDR-2 goal is to be backward-compatible with the initial DDR memories, providing an evolutionary
transition path. |
