Well, well, a 200Mhz what? How do you define your clock rate?
Its like statistics, you can make your numbers say anything you want.
How many meaningful designs do you know that run at 200Mhz that are not pipelined? The problem with FPGAs are that the LUTs cannot handle wide functions very well. To make wide functions you musr cascade or splice together multiple logic cells or CLBs, or LEs, or whatever.The trouble with this is that this eats up routing resources, which always are the Achilles heel of all FPGAs.You will always get better logic efficiency results with a CPLD than an FPGA. The LUT architecture has its own inherent warts.The whole thrust of going with Virtex, Actel and the rest of the bigger is better camp is to throw optimized blocks in a part and then connect them all together.This is fine for system type blocks, but for fast and wide logic, you just cannot touch a CPLD. Your 200Mhz number is really misleading.
Yes, at the heart of a CPLD is a switch matrix, but it allows a lot more routing flexibility, and a lot wider product term equations than FPGAs. So for fast, wide logic CPLDs are a better solution. And as we move down the process curve to lower geometry designs, this will get better. Do you really expect a 200Mhz 200,000+ gate device to be non
power consuming? CV2 my friend, you can't escape it. Sure CPLDs consume power, but so do FPGAs, especially at the speeds you are claiming. When was the last time you looked at a .25 micron 256 macrocell device? I think you will be surprised.
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