Sylvia,
sounds like you are a marketing person working for Lattice or possibly Vantis.? Not a bad guess considering the cheerleading and lack of due technical diligence. Your impressions of LUT performance are very aged. New generation LUT performance have ~1.0ns tpd thru the LUT. Add in some localized routing (either segment or local interconnect) for another 0.6ns and you can begin to see that despite being more granular, the LUTs can actually surpass CPLD performance even for wide functions.!! Here are multiple examples: 32bit CRC (3 levels 10 lcells), 32 bit Adder (32 lcells), deep Multiplexors (10 lcells,2 levels for 16:1), Even address decodes, and State Machines (1hot encoded). Newest generation FPGAs can actually hack it believe it or not.
What makes you think that the CPLD business is growing? Mcells shipped to the industry has surely increased, Revenue for CPLDs has been falling in the industry leaving a relatively flat line of constant dollars(check Dataquest). Lattice did however see flat revenus as their mixture of splds decreased while their cplds increased. Vantis however, I am not so sure saw that trend as their total revenue has been in decline. Max probably still pays the bills at Altera but I truly think that Flex product at their incredibly high growth rate (both LUTs shipped and Revenue) will cross over Max revenue sooner than you think - that at least is what Altera is publically projecting.
Lastly, for you and Lewis - currently IO is the pure bottle neck for all programmable logic. Debating Frequencies of much over 100mhz is almost comical. Tsu's are running ~3ns and Tco's are running ~4ns so as you can see IO performance is pretty much limited to just over 100mhz. Even Tpd requirements of <7ns can now be met with Virtex or Apex for fast asynchronous requirements.
That's about all, you can bet on your horse Lattice, Lewis and I will keep our bets on Altr and Xlnx to place and show. Thanks for the discussion.
-schlep |
