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Politics : Formerly About Applied Materials

AMAT 226.05

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Nov 14 9:30 AM EST

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To: Ian@SI who wrote (29832)	4/29/1999 10:26:00 PM
From: Katherine Derbyshire	Read Replies (1) of 70976

>>It just might be the crossover from producing 16 Mb chips to producing 64Mb and denser chips.<< Not sure I follow this. The ASP for a 64 Mb chip should be higher than for a 16Mb chip. Not 4x higher, but higher. Which is dropping, cost per chip (problem), or cost per megabyte (normal)? >>Thus fewer chips yield more MB; and fewer TER testers are required. And once the migration to 64Mb is complete, guess how many testers will be required for the 128Mb and 256Mb generations.<< Not necessarily true. Physical considerations place limits on just how fast you can test a memory cell. Therefore, larger arrays take longer to test. I don't know if it's one-for-one, though: I don't know if a 64Mb chip takes 4 times as long as a 16 Mb chip. It could take longer, since I think the smaller features require longer settle times. >>Then as the shrinks, reduce the silicon real estate required to produce those chips, guess how much extra process equipment is required to process fewer wafers.<< This is correct, as 1998 showed. Katherine

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