Ten,
I can tell you for sure that Intel themselves is moving towards
narrower, high-speed interfaces in future system designs. (An example would be
NGIO.)
Like mainframes did in the last five years, going from old, slow parallel copper to much faster serial fiber optic (ESCON) I/O.
I have a question on the implementation of RDRAM. I understand that the data rate of individual bit lines is 800 megabits per second out of the RDRAM chips (correct me if I'm wrong). Now, is data available on both edges of the signal? If that's the case, then are we talking 400 MHz (400 Mb/sec. X2 = 800 Mb/sec.) as the max. frequency on these data lines out of the RDRAMs? Are there any clock, or synch lines that switch at 800 MHz? What I'm really interested in finding out is what is the maximum frequency signals we're talking about as running around on a motherboard, from RDRAM to Camino chipset to Pentium III. The higher the frequency, the more the technology depends on a bulletproof transmission line, impedance matched board layout. Just wondering where the alligators are on this baby.
Seems like if RDRAM does require much faster switching data etc. lines, and therefore much more diligence in control of board layout characteristics, the competition, which seems to be coming back to life with a vengeance, would be all over this with a lot of FUD.
Tony |
