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Technology Stocks : Altera
ALTR 53.61+1.3%Jul 7 5:00 PM EST

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To: Sylvia Dupuis who wrote (2032)5/3/1999 12:32:00 PM
From: Lewis M. Carroll  Read Replies (1) of 2389
 
Sylvia, your arguments show that you know something about CPLDs.

Here's my argument: 200 MHz allows 5ns. That's three levels of on-chip logic in Virtex. Using all four LCs and local CLB routing allows, for example, an address decode of 13 address bits in 2.5ns. Take four of those and add a single LUT-4 in a fifth CLB and you pay +1 ns for routing, +1 ns for the LUT but you now have 52 (4 x 13) address bits in 5ns. That beats CPLDs. No, I'm not counting I/O pad delays - this is all on-chip. In the real world, you may have to get on the chip, do your decode and get back off in <5 ns. That limits you to only the smallest of CPLDs. If it's get on chip, do your decode and register the result then get off-chip, you still are limited to smaller CPLDs but Virtex can meet this (doing it now on a critical path for 64 bit 66MHz PCI). Remember, CPLDs get slower as they get bigger (not true with FPGAs - maybe 10K we'll see about 20K). Show me a big (>200 cell) CPLD without limited routing (Cypress 39000 has limited routing - looks like an FPGA with big CPLD CLBs instead of X/A LUT4 CLBs) that can do a wide function at 200MHz...

Also, all CPLDs are limited in speed first by their block fan-in (<20 for Lattice, Vantis, 36 for Altera, Cypress, 54 for Xilinx), and second by the number of dedicated PTerms per macrocell (Cypress is best here at 16, Lattice at 4, Altera, Xilinx at 5, Vantis at 4 I think). There are various schemes for increasing product terms used by a macrocell (parallel expander, shared expander, etc.) but all incur a timing penalty.

Your fundamental argument is that LUTs cannot handle wide functions well and must be cascaded. True, but Virtex allows you to do just that at blinding speeds - my argument. How do you define "Logic efficiency?" Compare prices - FPGAs give you far more logic per dollar than CPLDs. It's almost universally true that if you can do the same function in either an FPGA or a CPLD, the FPGA function will cost less (given that an equal price FPGA and CPLD is available).

P.S. You wouldn't be Ed using your wife's account would you?
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