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Politics : Formerly About Advanced Micro Devices

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To: Scumbria who wrote (57111)	5/3/1999 5:44:00 PM
From: Tenchusatsu	Read Replies (2) of 1572565

Jim: Is this the case with the P6 core too? Scumbria: I don't believe so. Willamette will very likely add clocks to the L1 cache access for the same reasons as K7. Just to clarify things, guys. The larger the L1 cache, the slower it is. The Pentium II and Pentium III is still sticking to a 32K L1 cache, which is why the P6 core doesn't need to add clocks to the L1 cache access. The K7 is going with an oversized 128K L1 cache. Since the K7 is also architected for high MHz, it has to add a clock or two to the L1 cache access. This creates longer latency when you access the L1 cache, but the hopes are that the reduced accesses to slower L2 cache makes it a good trade-off. So in other words, adding a few clocks to the L1 cache access isn't the "key" to high MHz. Rather, it's just a way to grow your L1 cache so that you don't impact the MHz. As for Willamette, I don't know what the heck they're going to do. Intel already said that one of the things Willamette will feature is an instruction trace cache. I asked my old roommate (who's a Willamette guy) to explain the trace cache for me, and he couldn't do it. :-( Tenchusatsu

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