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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (57112)5/3/1999 5:58:00 PM
From: Scumbria  Read Replies (3) of 1572559
 
Ten,

Just to clarify things, guys. The larger the L1 cache, the slower it is. The Pentium II and Pentium III is still sticking to a 32K L1 cache, which is why the P6 core doesn't need to add clocks to the L1 cache access.

The small P6 cache helps the situation, but still implies that clock speed is limited by L1 cache access. Who knows how fast P6 would run with an additional pipeline stage for L1 access?

Your statement that a large cache is slower only addresses part of the L1 problem. L1 cache speed has two major issues. One is tag lookup/compare and the other is data array access (which is largely a function of the array size.) Adding additional clocks for L1 access fixes both of these problems.

I expect that K7 MHz will cause Intel a lot of problems.

Scumbria
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