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Politics : Formerly About Advanced Micro Devices

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To: Tenchusatsu who wrote (57112)	5/4/1999 10:54:00 PM
From: grok	Read Replies (1) of 1572630

re: <Intel already said that one of the things Willamette will feature is an instruction trace cache.> A trace cache stores instructions in the order that they are executed instead of the order that they are stored in memory. It is effective in wide issue superscalar. When you're issuing 6 or more instructions on the average you've got at least one taken branch in the group and all instructions after the taken branch are useless with a conventional cache. If you're issuing 12 instructions you've probably got two taken branches in the group making 12-issue very ineffective with a conventional cache. The trace cache allows you to issue 12 instructions from the execution stream (assuming that execution is repetious). Intel has been investigating trace caches for IA-64 since they plan very wide issue (I think Merced is 6-issue that the next one is 12-issue). Looks like they decided that it was also useful for x86.

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