SIA's '98 roadmap revision hits the Web, predicting 1-terabit DRAMs by 2014
A service of Semiconductor Business News, CMP Media Inc.
Story posted 5:15 p.m. EST/2:15 p.m., PST, 5/5/99
By Jack Robertson
WASHINGTON--The Semiconductor Industry Association publicly released its 1998 revision of the SIA technology roadmap on the World Wide Web today. The document moves major technology targets for semiconductors ahead by one year, compared to the SIA's 1997 U.S. roadmap, and for the first time, it predicts that 1-terabit DRAMs will be introduced in 2014 using 0.035-micron processes.
Last year's revision started out as a fine-tuning of the SIA's 1997 roadmap, but when it was finished in December, the unofficial update turned into an extensive revision of the document. Technology generations were moved up by one year, and about half of the 63 published tables in the 1997 document were revised, according to SIA officials earlier this year (see Jan. 19 story).
The 1998 document is also the first SIA roadmap produced with international input. As a result, the 1998 revision has become the first International Technology Roadmap for Semiconductors (ITRS). It is available to the public worldwide on the Web at: itrs.net
The revised roadmap confirms earlier SBN reports that the 0.15-micron chip generation has been dropped from the document as an official technology node. All other generations were moved up one year. The 0.13-micron technology node for DRAM half-pitch is now set for 2002, the 0.10-micron generation in 2005 and 0.07-micron node is in 2008.
Each generation of DRAM has advanced ahead by one year as well. The first 1-gigabit DRAM samples are slated to be out by the end of 1999, and 4-Gbit samples are set for 2002. Samples of 16-Gbit DRAMs are expected to be initially developed by 2005 and 64-Gbit by 2008.
The new roadmap adds 2014 to its technology tables for the first time. It calls for a 0.035-micron technology for DRAMs and 0.025-micron isolated lines for microprocessors. The roadmap predicts that this technology generation will be used to make 1-terabit DRAMs with 1 trillion bits on a chip. Microprocessors will have 390 million logic transistors/cm2 using this class of process technology in 2014, according to the revised roadmap.
A more immediate change in the revised roadmap can be found in the calculation of cost-per-bit for DRAMs, which drops to 40-microcents in 1999 from 60-microcents projected for this year in 1997 roadmap.
Also the new roadmap dropped the cents-per-pin package cost for semiconductors this year to a range of 70 cents to $2.52. It was a range of $1.25-2.80. In 2002, the packaging cost is now estimated at range of 60 cents to $2.16 vs. the 1997 estimate of $1.15-$2.30.
Part of the packaging cost reduction is due to scaled-down projections of I/O connections. The new roadmap estimates that in 1999 the number of chip-to-package pads for high-performance microprocessors will reach 1,867 -- a year earlier than the previous projection, which targeted the year 2000 for that level of complexity. For value-priced MPUs, the number of chip-to-package pads this year drops to 934 from 975.
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