Dean,
Can you comment on this article from EE Times, and whether any of the named companies are using ATMI technology?
Memory designs embrace the exotic
By David Lammers and Yoshiko Hara
SAGAMIHARA, Japan -- In an attempt to sustain the rapidly increasing density of DRAM technology, the latest research is moving into more exotic materials systems, such as silicon-on-insulator (SOI) and ferroelectric capacitor designs. Logic design is also slated for a makeover, with forward-looking multilevel logic allowing more information to be stored on a single DRAM capacitor.
Since memory-chip design usually breaks new process ground for silicon technology in general, the experimental research may herald a new era of "post-binary" logic supported by the integration of new materials into today's standard silicon systems.
At the International Solid-State Circuits Conference last month, NEC broached the 4-Gbit density level with a file-memory DRAM that uses multiple voltage levels to store 2 bits in each cell, and Mitsubishi Electric unveiled a 1-V DRAM that takes advantage of SOI technology. Meanwhile, Toshiba Corp.'s Materials and Devices Laboratory is investigating a novel, ultrathin barium strontium titanate capacitor structure that could realize DRAMs that are 4-Gbits dense, according to researchers there.
The 4-Gbit DRAM fabricated at NEC's Sagamihara development center required the development of a sense amplifier capable of reading four levels of capacitance. That, in turn, depended on a better dielectric material in the cell capacitor: barium strontium titanate. The material not only is good at storing charge but also supports the ferroelectric effect, which, like non-volatile magnetic media,
switches between two stable polarization states. Currently, the ferroelectric property is buying designers more capacitance in a smaller area than can be achieved with conventional materials.
Tatsunori Murotani, leader of the design team, said multilevel cell (MLC) technology in flash memories depends on varying threshold voltages. That is not to be confused with MLC technology as applied to DRAMs, where the sense amplifier detects four levels of capacitance: ground, one-third of Vcc, two-thirds and Vcc. Those storage levels represent 00, 01, 10 and 11.
The NEC design depends on a complex sense amp circuit, which senses the more complex storage levels. Though the circuit is larger than conventional designs, one-third as many are needed to achieve an equivalent density. The new architecture uses a second bit line, separated from the usual, single line, to create two sections linked by a transfer switch in order to maintain easily determinable capacitance ratios.
Each memory cell stores 60 fF of charge -- three times the conventional capacitance. That required the first-time use of barium strontium titanate as the cell dielectric material.
Takashi Okuda, a senior manager at NEC's Sagamihara laboratories, said NEC will be able to use nitride oxide with hemispherical grain (HSG) silicon as the dielectric up to the 1-Gbit level. The multicell approach to 4-Gbit density DRAMs will require moving to barium strontium titanate.
By storing 2 bits in each cell and reducing the number of sense amps by two-thirds, the 4-Gbit density can be achieved without creating a pizza-sized die. First access speed is sacrificed, but the more important concern is whether high reliability levels can be achieved with the notoriously fickle MLC approach.
If reliability can be assured, then MLC 4-Gbit DRAMs also could be used in applications where data security is essential, such as in financial databases, Okuda said.
NEC fabricated the experimental devices using a 0.15-micron process with electron-beam lithography. Not all of the bits are functional, but the entire chip -- at 985.6 mm2 in size -- was fabricated. Okuda said a very aggressive outlook would see initial sample quantities of the 4-Gbit generation devices starting in 2002 or 2003, using 0.1- or 0.09-micron CMOS for commercial production. However, that road map could easily slip, he said.
"We will need DRAMs with large capacity for virtual reality systems and the huge worldwide databases of credit and other financial information," Okuda said.
Hajime Sasaki, in charge of the electronic devices division at NEC, said the MLC approach will be useful as a "file memory for graphics." And he noted that NEC was the first to have a 4-Gbit density design at ISSCC.
Mitsubishi Electric Corp. turned to SOI technology to deliver a 16-Mbit DRAM that operates with a 1-V power supply. "In the year 2000, most electronic products will run on a power of 2 V to 2.5 V and portable units will require 1.5-V to 1.8-V operation. This 16-Mbit DRAM operates at high speed, using voltages much lower than those requirements," said Shinji Komori, a design manager. The small threshold swings and smaller parasitic capacitance levels possible with SOI wafers helped Mitsubishi to deliver excellent performance: a 46-ns access time.
Simox-type SOI wafers have a layer of silicon oxide implanted below the crystalline silicon. The transistors fabricated on SOI wafers dielectrically isolate the body (back gate) with the silicon oxide
layer. Mitsubishi introduced a voltage control technique for the body structure in SOI-based circuits. Komiya said this structure eliminates current leaking to the substrate and to the adjacent transistor. Mitsubishi engineers minimized leakage current in the channel by controlling the body voltage.
The SOI transistor operates in two modes, a partially depleted (PD) mode, or a fully depleted (FD) mode, in which no holes or free electrons exist in the body. The former is used to drive high currents, while the latter reduces the leakage current in the channel when the gate is off.
The engineers optimized the thickness of the SOI layers and the channel dose, so that the FD-PD mode transition occurs in the small range of the body bias voltage.
By controlling the body voltage, the transistor's operation can be switched from the PD and FD modes. The small leakage current and good drive characteristics come at the price of using SOI wafers, which cost many times more than bulk silicon wafers and whose quality in the silicon layer is inconsistent.
The Mitsubishi device shows that the pain of working with SOI materials may be worth the trouble for portable applications. The 16-Mbit device revealed at ISSCC operates about 20 percent faster than conventional SOI devices without the body control circuit. The voltage-control switch can be added just by changing the layout and does not involve additional process steps. The die size is 154 mm2, slightly larger than DRAMs made on bulk silicon, but the size can be reduced, said Komori. Mitsubishi has no immediate plans to market the device, but is considering using the technology for 16-Mbit DRAMs for portable systems.
Toshiba also is looking into barium strontium titanate as a capacitor material for the 4-Gbit DRAM generation. The work has revealed an interesting property of very thin films of the material when grown on lattice mismatched substrates -- an ability to use lattice strain to tune the ferroelectric properties of the material. Ferroelectric switching depends on a particular geometric arrangement of electrons in the solid that form dipole pairs that flip their polarization in much the same way the magnetic domains switch in ferromagnetic materials. While that geometry is fixed by the lattice structure of bulk samples of the material, thin films can be stretched to alter crucial ferroelectric parameters. As a result, the information storage properties of the material can be tailored by growing thin films on different substrates.
The Toshiba researchers have used that strategy to build a prototype 4-Gbit DRAM cell that features a 30-nm-thick film of barium strontium titanate on an epitaxial strontium ruthenium oxide layer. Not only is the film the thinnest to be used in a DRAM capacitor design, but it also showed record capacitance levels. The cell architecture uses a ferroelectric capacitor on the bit line, which is connected to the drain of an FET via a silicon plug. Several buffer layers are first grown on the top of the plug, followed by the barium strontium titanate film.
-- Additional reporting by Chappell Brown. |
