this note just from a software/theory guy...
really, having formally absorbed only the minimum from the e.e. hardware design side at the big u. some years ago. so as chip
sleuths y'all have guesses as good or better than mine.
as for the notes themselves [you were v. busy on OUM during my hiatus,
indeed]:
3491 clean room
3509 jukebox
3513 clean room/multistate
3520 model studies
3526 speed/power
3527 angstroms/resistance
3587 carver mead
all are keenly observant, myself finding the 3520/26 questions key.
(of course clean rooms are used to keep the dust motes away from any micron-level work -- this is not "roll-to-roll" manufacturing
in any sense.)
yes, we need progress reports on how studies have matched test chips!
e.g. for ferroelectrics, look at a web page like:
eecg.toronto.edu
showing university work with pictures and references. but ECD
plays everything so secretly, arggh. has any sort of test chip been
built? where, at a university lab/clean room? it is so typically
strange that little ECD stuff is reflected in journal publications,
where public relations b.s. is simply not allowed.
about "the competition", i must study further to judge, but ramtron
has >160 patents on ferroelectric RAM and multiple design/development partners yet still is a fifty-cent stock.
IBM is a power to reckon with, yes (i need to read that sci. am. piece).
speed/power product -- i tried to calculate typical chip power from
the joules per bit, but fell short, temporarily. yup, we need to
know whether if it is used like a typical RAM at 30-40 ns it
doesn't fry.
i'll try to contribute more later, but let's concentrate on simple
FLASH replacement first, before claiming ORAM will fly the speed
of SRAM with the low power of magnetic RAM and the cost of DRAM.
and, what does sandisk think? or your local university engineering professors? |
