TSMC boosts spending to add 0.18-micron capacity
A service of Semiconductor Business News, CMP Media Inc.
Story posted 12:15 p.m. EST/9:15 a.m., PST, 5/14/99
By David Lammers
SAN JOSE ( ChipWire/EET) -- The board of Taiwan Semiconductor Manufacturing Co. Ltd. voted on Tuesday to raise the foundry's capital expenditures budget to $1.265 billion for 1999--a jump of $446 million over the company's February plan--to seed the way for 0.18-micron manufacturing.
TSMC's loosening of its purse strings comes as the fabless semiconductor industry--the traditional base of the largest foundries--starts to compete for scarce wafers with the traditional giants of the industry, such as Motorola Inc.
Roger Fisher, a vice president of worldwide marketing at TSMC, said the raised figure is needed to support the ramp of 0.18-micron capacity in Taiwan and, later this year, at the Wafer Tech joint-venture fab in Camas, Wash. Operated by TSMC and partly owned by Altera Corp., Analog Devices Inc., and others, Wafer Tech is processing more than 10,000 wafers a month and will be at 90% capacity by summer.
"We see significantly higher demand today than at the beginning of the year, and demand is increasing faster than our capacity increase," Fisher said. "Our utilization rate at all of our fabs is already about 90%, so we are increasing our capital-spending plans and pulling in capital-equipment deliveries from our major equipment vendors."
TSMC was conservative last December, planning to spend only $715 million in 1999 in Taiwan, Camas and at a Singapore fab jointly owned with Philips.
The TSMC board voted in February to up the budget to $976 million, and the latest revision takes spending to 65% more than called for in that plan.
The increase will support a 14% rise in wafer capacity this year and a 30% increase in 2000, to 2.423 million 8-inch-equivalent wafers for the year.
TSMC expects that in 2000, about a quarter of its capacity will be "0.18 micron-ready." About 34,000 wafers will be done at 0.18 micron this year, but that will accelerate to 600,000 next year as 0.18 micron becomes the most cost-effective solution for customers with performance and power-consumption needs, the company said.
"We are beginning to process wafers now at 0.18-micron design rules, which gives us a 100% improvement in gate density, from 50,000 gates per millimeter squared to 100,000," said Fisher. "And speed improves by about 30%, to the 300-400-megahertz range for logic and 500 MHz for our SRAM cell."
The process yields an SRAM cell size of only 4.6 square microns--about the same as the cell size IBM Corp. achieves with the aid of local interconnects, which TSMC does not use, said Kenneth Chen, a technology marketing manager at TSMC.
Rather than emphasize the effective gate length, Chen said that metal pitch is the more important figure of merit for TSMC. The company has a fully contacted M1 (first-layer metal) pitch of 0.46 micron, which he said compares with 0.49 micron by IBM and 0.50 micron by Intel Corp., according to their published specifications. TSMC rates its gate length at 0.16 micron for the 0.18-micron process, but the Leff will shrink to 0.13 micron as the process is modified next year.
TSMC also will offer a dual-gate oxide approach so that designers can integrate higher-voltage I/O circuits, often at 3.3 volts, with the lower-voltage cores of 1.8 V and 2.5 V.
TSMC is developing an embedded flash technology with Silcon Storage Technology Corp. of Sunnyvale, Calif., and an embedded DRAM technology with Vanguard Semiconductor in Hsinchu, Taiwan, which it partly owns.
"At 0.18 micron, people will move to more of a system-on-a-chip style, and so we have to offer more embedded memories and mixed-signal library support," Chen said.
Fisher said some semiconductor companies, such as Intel, design a process to support MPUs that command average selling prices of $100 or more. But many of TSMC's customers bring ICs to their target markets at $20 to $40.
"By early next year at the latest, there should be some cost savings in using 0.18-micron design rules, with the condition being for ICs which are not pad limited," he said.
To keep costs down, TSMC will offer copper interconnects only on the two thick, routing metal layers that connect functional blocks, sticking with aluminum for the shorter metal links between transistors. True low-k dielectric materials are not available for inter-metal-level insulation.
"Aluminum can be integrated with some of the low-k materials, but not copper," said Fisher. "We see perhaps a 15% improvement in adding two layers of copper, but for all-level copper, this is not the time. By the 0.13-micron generation, we will be there."
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