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Politics : Formerly About Advanced Micro Devices
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To: grok who wrote (58422)5/17/1999 1:37:00 PM
From: Tenchusatsu  Read Replies (1) of 1574890
 
<Nope. The 21164 uses a single cycle L1 and a huge on-chip L2 with many cycles (can't remember how many but it's alot).>

I said half of what you said. I already knew that the 21164 had a larger on-die L2 cache whose access times are much longer. The problem is that since the 21164's L1 cache is so small, too many accesses were going to the L2 cache, then the off-chip L3 cache.

So Digital goes with an oversized multi-cycle L1 cache for the 21264. Yet even with a lengthened L1 access time, it's still 18% slower in clock speed than the 21164. Of course, the performance is much better even at the slower clock speeds, but it goes against Scumbria's argument that a multi-cycle L1 cache is the key to higher clock speeds.

My assertion still holds, that adding cycles to the L1 access time is only a way to increase the L1 cache without impacting the clock speeds too much. This is the case in the 21264 and in the K7, because both of them have oversized 128K L1 caches.

<The problem with the 21164 is that the on-chip L2 access is so long that a big L1 with two cycle access beats smallL1+hugeL2. Of course, I doubt that the last word is in on this subject.>

It's not the last word. Merced will have on-die L0 and L1 caches, and an off-chip L2 cache. I'm willing to bet that the L0 access time is a single cycle, though I have no idea how large the L0 cache will be.

Tenchusatsu
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