The Inherent Limitations of Either "More Boxes" or "Bigger Boxes"
The creation of new scaleable TeraPOP architectures to handle tomorrow's traffic levels will require a dramatic departure from yesterday's technological approaches, which generally have consisted of either adding more boxes or trying to build bigger single-backplane boxes. As has been demonstrated above, the traditional approach of simply adding more limited-scale conventional routers carries with it an exponential increase in overall network complexity and Layer 3 software overhead that eventually bogs the network down in its control logic.
To reach the required capacity at major Internet concentration points, such as SuperPOPs and IXPs, carriers have had to build complex networks within networks, while experiencing ever-diminishing efficiency from each incremental addition.
On the other hand, the maximum speed of conventional routing systems is inherently limited by the speed of the semiconductor technologies used to implement them and the aggregate bandwidth of their internal backplane architectures.
From a semiconductor standpoint, even the continued march toward finer process geometries and the advent of high speed processes, such as Gallium-Arsenide (GaAs) and Silicon-Germanium (SiGe) are only keeping chip-level speeds up to the growth pace predicted by Moore's Law. Even if semiconductors do continue doubling in speed every 18 months, that simply means that chip-level performance is falling further behind every day as the Internet continues to grow at a sustained rate 3 to 6 times greater than the increases in semiconductor speeds.
Backplane bandwidth constraints have traditionally posed the major barrier to simply creating faster versions of conventional router architectures. Initial router designs were based on single bus architectures, which provided the most straightforward and robust implementations for limited scale systems. Although the evolution of dual-bus and crossbar structures has done much to improve backplane throughput, the critical issue is now shifting away from the raw backplane speed of such single-box systems and toward the need for scaling up to handle many more ports than any single box can support.
The challenge of effectively terminating thousands of WDM channels from hundreds of OC-48 and OC- 192 connections goes well beyond the capacity of any single monolithic system. For instance, as the 200,000+ voice lines between core Central Office installations transition instead toward thousands of DSL lines, high-speed cable modems and wireless connections, the new infrastructure will require hundreds of OC-48 and OC-192 optical ports to carry the traffic over WDM channels.
No matter how big or fast the backplane, a finitely-defined, single-box system will always be fundamentally constrained by the amount of physical real estate in the box for providing port connections. This port-density limitation cannot be overcome simply by attempting to aggregate together a number of such monolithic individual systems because the sheer complexity of load-sharing port traffic between the separate boxes quickly becomes prohibitive.
The emphasis for next-generation systems will have to be on creating inherent capacity to cost-effectively terminate the maximum number of ports within each box and then to gracefully and economically be able to expand the overall system to encompass additional capacity. In essence, the basic architecture for tomorrow's backbone-class, terabit-level devices will need to transition from the concept of a "single box" to that of a "single system" in which all system components can be mutually optimized and smoothly scaled. |
