Walt, with regard to the OUM, here is a (business Wire) news release about an upcoming competing technology from HItachi (taken from the Hitachi.Com web site). In simple terms, Hitachi adds a second, special transistor in place of the usual capacitor. They indicate that "in principle" this arrangement can be made to provide non-volatile storage.
Seems to me that adding a second transistor is more complicated than simply adding a special resistor, as in the OUM. However, the HItachi device is, IM lay O, more of a competitor than the IBM "spintronic" device.
Am I just paranoid, or is there some nasty purpose behind the recent IBM and HItachi announcements? These news releases seem premature since the devices are still not ready for production. Are the big guys trying to create FUD in the minds of potential OUM investors?
BW1038 MAY 18,1999 7:17 PACIFIC 10:17 EASTERN
( BW)(CA-HITACHI)(HIT) Hitachi and Cambridge University Achieve Breakthrough in New Generation Semiconductor Memory
Business Editors/Technology Writers
LONDON--(BUSINESS WIRE)--May 18, 1999--A team of scientists from Hitachi (NYSE: HIT) and Cambridge University today announce a breakthrough in semiconductor memories for the new generation. The creation of a new memory device named 'PLEDM(TM)' - Phase-state Low Electron(hole)-number Drive Memory, will have major implications for computer, communication and electronic systems.
PLEDM(TM) will enable instant recording and accessing of a massive amount of information: for example, all the images & sounds of an entire movie can be accessed from a single PLEDM(TM) chip. In addition, PLEDM(TM) consumes very little power, making equipment such as mobile phones and computers lighter and more economical.
The ongoing quest to develop smaller and faster memories is leading to chips with increasingly complicated structures and higher power consumption. DRAMs are currently used as main memories in computers because of their high-capacity and high-speed. DRAM technology, however, has an inherent drawback - namely the contradictory requirements of further reduction in cell size and maintenance of S/N (signal-to-noise) ratio large enough to guarantee operation.
Scientists at Hitachi and Cambridge University have, therefore, been focusing on developing a totally new type of cell structure to overcome this drawback. Conventional DRAMs consist of one-transistor and one-capacitor cell, the new PLEDM(TM) cell uses instead two transistors to make a 'gain cell' in a smaller area.
The newly developed transistor, PLEDTR(TM) - Phase-state Low Electron(hole)-number Drive TRansistor -, is stacked onto the gate of a conventional MOSFET and has unique electrical characteristics to allow the PLEDM(TM) cell to work. The integration of one transistor onto the gate of another is a world first and has allowed the present breakthrough to be achieved.
The PLEDM(TM) cell is as small in area as just one transistor - with a read / write time less than 10nsec. In addition, the gain provides a large signal even in low-voltage operation, leading to reduced power consumption.
The cell can be manufactured with standard silicon processes. The performance of the PLEDM(TM) cell will be improved further with decreasing feature size in the future.
The PLEDM(TM) is a promising candidate for the multi-Gbit memory chip which is scheduled to become available early in the next century. With further development, PLEDM(TM) could also solve the current performance trade-offs experienced with the two existing types of memory: the DRAM - high-speed but volatile memory (memory lost when power switched off) and the FLASH - slower but non-volatile (memory retained when power switched off).
In principle, it is possible to make a fast non-volatile PLEDM(TM) cell by modifying the barrier-structure in the channel, and the scientists are confident that many of the present day data storage devices (eg: computer hard disk drives) could be replaced by PLEDM(TM) in the future.
Professor Haroon Ahmed, Professor of Microelectronics at University of Cambridge, said: "This project is likely to be a commercially exploitable output from the Hitachi and Cambridge University research collaboration, which, over the last ten years, has produced many scientific breakthroughs. It represents a significant step in the path to an electron-number scalable RAM cell and eventually to high-speed single electron device technologies."
Dr. Yasutsugu Takeda, Board Director, Hitachi, Ltd., said: "When we started the Hitachi Cambridge Laboratory ten years ago we believed that a new interdisciplinary research project should rely on a common research platform between industry and university and should be run based on openness, fairness and return to the community. We are very pleased that our collaboration has resulted in such a fruitful output."
Notes to editors:
Definitions of key terms:
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
DRAM - Dynamic Random Access Memory
FLASH - block-erase electrically erasable programmable read-only
memory
Gain cell - memory cell amplifying a small storage charge in
itself
Further technical details:
The DRAM cell consists of one switching transistor and one capacitor. This cell has no gain and, therefore, currently requires a large cell-capacitor to produce a sufficient sense signal. The PLEDM(TM) cell consists of two transistors. This cell has gain and a large S/N ratio, and thus does not need the separate capacitor required in DRAM cells.
PLEDTR(TM) has multiple barriers in the channel, which are formed by extremely thin insulating layers. The barriers are controlled energetically by applying a bias to the side gate electrodes. This novel transistor has been fabricated successfully on silicon dioxide substrates using a standard 0.2um silicon process. The critical barriers were formed by using thermal nitridation of silicon resulting in ideal ultra-thin insulating layers with well controlled thickness of about 2nm. The transistors with an in-plane area of 0.2 x 0.4um2 have shown:
1. ON currents as large as 1uA which achieve write times less than
10nsec
2. OFF currents less than the limit of standard DC measurement
systems (1fA) which guarantee refresh times longer than 0.1sec
3. Threshold voltage deviations of
The new transistor enables construction of a novel high-density PLEDM(TM) array with a cell size smaller than a DRAM cell.
Notes to editors
Hitachi Europe Ltd., is a wholly owned subsidiary of Hitachi, Ltd., Japan. It has operations throughout Europe, which provides sales, marketing, technical support and research & development. For more information please visit Hitachi Europe's Web site at hitachi-eu.com.
Hitachi, Ltd., headquartered in Tokyo, Japan, is one of the world's leading global electronics companies, with fiscal 1997 (ended March 31, 1998) consolidated sales of 8,417 billion yen ($63.8 billion/a). The company manufactures and markets a wide range of products, including computers, semiconductors, consumer products and power and industrial equipment. For more information on Hitachi, Ltd., please visit Hitachi's Web site at hitachi.co.jp.
/a At an exchange rate of 132 yen to the U.S. dollar.
--30--HK/na*
CONTACT: Hitachi Europe Ltd
Masao Takebayashi / Jo MacGovern, 011441628 585 000
mtake@hitachi-eu.com / joanna.macgovern@hitachi-eu.com
or
Citigate Dewe Rogerson
Patrick Evans / Stephanie Barrett, 011447171 638 9571
peva@dewrog.co.uk / sbar@dewrog.co.uk |
