**NEC Announces World's Largest System-On-Chip ASIC Chip 03/11/97
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TOKYO, JAPAN, 1997 MAR 11 (NB) -- By Martyn Williams. NEC Corporation [TOKYO:6701] has announced the development of, what it says is, the world's most highly integrated system-on-chip ASIC (application specific integrated circuit). The new chip uses 0.25 micron technology, which means more components can be squeezed closer together.
System-on-chip ASICs allow electronics device manufactures to integrate lots of different functions, called "cores," onto a single chip and thus have an entire system on a single chip. Previously the system would have required several chips.
This technique leads to advantages for device developers because a single chip requires less power, 0.02 micro Watts at 1.8 volts, in addition to less space. The combination of several chips into a single one also means less weight. All three are important aspects of design in mobile and hand-held devices and will lead to smaller and lighter devices that have a greater battery life.
The new NEC chip comes with a variety of cores, all designed around the area of multimedia. The include those for communications use, such as Ethernet, ATM (asynchronous transfer mode), ASDL, and VSDL, in addition to consumer cores, including a MPEG-2 (Motion Picture Experts Group type 2) encoder and decoder. Other cross application and general use cores, like a phase locked loop, DRAM memory, and flash memory are also available. By integrating the various cores, it is possible to produce a complete system that, for example, takes incoming data from an Ethernet line and produces decoded MPEG-2 video, all on a single chip.
The use of 0.25 micron technology, which indicates the minimum space that is needed between tracks and components, allows 4.4 times the previous best system-on-chip ASIC technology of NEC of 0.35 micron, said company spokesman Aston Bridgman. A system clock speed of 300 megahertz is possible with the system.
Sampling of the new ASIC will begin in June, with mass production beginning in October, said the spokesman. Pricing is dependent on the configuration, but a chip with maximum of 3.14 million gates step, on 420 pin BGAT and production of 10,000 units per month would be 44,800 yen (US$369) each. Non-recurring engineering fees of 50 million yen ($411,500) are also applicable.
Exchange rate: $1 = 121.50 yen
(19970311/Press contact: Aston Bridgman, NEC Corporation, +81-3-3798-6511, fax +81-3-3457-7249; Reader contact: nec.co.jp /Reported By Newsbytes News Network: newsbytes.com /NEC970311/PHOTO)
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