SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (59307)5/23/1999 8:06:00 PM
From: Gopher Broke  Read Replies (1) of 1572958
 
No doubt you can get performance boosts at the expense of complexity. In the scenario you describe, assuming the processor has dual paths for all computations (including the not-so-obvious assumptions like the compiler will need twice as many general purpose registers to be able to perform the same level of register optimization since it is now sharing them between two threads) then you can get twice the throughput over those sections of code where the thread instructions can be totally paralleled.

FWIW my prediction is that it will work out cheaper to get the same throughput by running those two threads on a dual processor system.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext