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Politics : Formerly About Advanced Micro Devices

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To: grok who wrote (59931)5/28/1999 1:43:00 PM
From: Scumbria  Read Replies (1) of 1574045
 
KZ,

The thing is that today's micros only usefully dispatch and retire about 1 instruction per cycle. So getting this up to 2 would represent a massive breakthrough.

The average is 1 per cycle retirement. If dispatch was limited to 1 per cycle, the average would go down.

The problem that academic CPU types have had is that they tend to focus on the instruction sequencer, and ignore the overwhelming impact of the DRAM subsystem. How many dataflow architects have been sorely disappointed by the 1.0 IPC when the silicon came back?

Scumbria

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