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Pastimes : Dream Machine ( Build your own PC )
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To: Clarence Dodge who wrote (7573)5/28/1999 8:01:00 PM
From: Sean W. Smith  Read Replies (2) of 14778
 
Spots, Clarence, and All

still way behind reading messages here. busy at work trying to tape
out my latest ASIC and plan this years TA conference. The last few
months I have been designing a Double Data Rate (DDR) SDRAM
controller for our latest ASIC. I have learned a ton about SDRAM in
general as well as ECC. My design utilizes 8 bit SECDED ECC
Algorithm on 64 bit sdram interface. SECDED = Single Error
Correction, Double Error Detection.... Below I will post an summary
of what I wrote in the ASIC spec about the improved reliability of
ECC. I will not go into the math nor the assumptions made for bit
error rates etc. Look at the relative difference not necessarily the
absolute values.

-------------------------------------------------------------------

ECC Diagnostics
The following diagnostic mode is provided to determine whether the
Error Detector and Corrector or the Memory is failing:-

Checkword is written into a register by the CPU while the data input
remains transparent. This allows the CPU to supply various data words
against a fixed checkword. Error flag functionality can be verified.

Performance
In the simplest terms, the greater the number of memory IC's in the
system, the greater the probability of failure. ECC drastically
increases system MTBF with single bit error correction.

Average number of Uncorrectable Errors: Parity vs SEC-DED
Time (1000hrs) Parity SEC-DED
0-10 49 3.2
0-20 81 5.2
0-30 111 6.9
0-40 168 9.3
0-80 253 13

Source: 1984 IBM Journal of Reasearch and Development, Chen, C.L. and
Hsiao, M.Y. (1984). Error-Correcting Codes for Semiconductor memory
Applications: A State-of-Art Review. IBM J. Research and Development.

DRAM manufacturers often specify soft error rates in terms of FITs
(failures in time). Assuming a 200FIT rate on a 64Mbit DRAM. One FIT
is defined as 1 failure in 1-billion device hours.

NOTE: The MTBF given below is for comparison purposes only and should
be used as a guideline only. It assumes an extremely simplified
environment. The authors of this document take no responsibility for
any misinterpretation of this data.

MTBF of 256MB Memory System with 8-bit parity (no ECC)
MTBF for each 64Mbit DRAM chip is 10^9/200 = 571 years
MTBF for a 256MB (32Mx72) DRAM system = 571/36 chips = 16 years

A memory system without EDC assumes a catastrophic system failure
each time a single bit error occurs. [Failures due to higher order
(dual, 3-bit, etc.) errors can be safely ignored due to the
overwhelming dominance of single bit errors over the higher order
errors]

MTBF of 256MB Memory System with 8-bit ECC:
Assuming EDC corrects all single bit errors, system failures due to
dual bit errors become dominant. Neglecting failures due to higher order errors, the MTBF approximation becomes:

MTBF (with ECC) = MTBF (without ECC) * sqrt(pi * #memory words / 2)
= 16 * sqrt (pi * 32M/2) ==> 113437years

Sean
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