Interesting patent: Matsuhita Electric Corporation of America
164.195.100.11
quote:
Various types of data are stored in the memory 120. In the exemplary embodiment of the invention, the memory 120 holds the MPEG-2 encoded bit-stream, two anchor frames, the frame being decoded and at least a portion of the frame that is being displayed. Even with the wide-bandwidth and concomitant high transfer rate of the RAMBUS memory 120, it is desirable to control the writing into and reading from the memory to ensure that data held in the memory can be fetched from the memory when it is needed and written into the memory as needed, without delay.
As shown in FIG. 2, the memory 120 is divided into two channels, each of which is connected to a respectively different RAMBUS application specific integrated circuit (ASIC) cell (RAC) 172. The RAC's 172, in turn, are coupled to a RAMBUS ASIC cell (RAC) interface 170. The RAC interface 170 provides 128 parallel bits of data to, and receives 128 parallel bits of data from the various elements of the decoder circuit via a single memory port as described above. The bus between the RAC's 172 and the memory 120 is a bidirectional bus having a clock rate of 250 MHz. In the exemplary embodiment of the invention, this memory port is expanded internal to the decoder IC 110 to include separate input and output busses. It is contemplated, however, that a single bidirectional memory bus could be used for the internal memory bus.
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