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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: fyo who wrote (60730)	6/6/1999 7:42:00 PM
From: kash johal	Read Replies (1) \| Respond to of 1572946

Fyodor, Re: " Fact: The K7 will use an external 2.5V supply. Fact: The K7 will regulate this down to 1.6V internally." Please don't post a bunch of crap. The K7 is in AMDs 0.25 or at best 0.22 process. The power supply will be in the 2.2-2.5V range. The 1.6 is for the PLL and only used for clock generation. If AMD runs the chip at 1.6V we will be lucky to see 300Mhz speeds!!! Regards, Kash

To: fyo who wrote (60730)	6/6/1999 8:24:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1572946

Re: "Fact: The K7 will use an external 2.5V supply. Fact: The K7 will regulate this down to 1.6V internally" It is customary to present some supporting data when making claims of fact, however we are used to AMD type claims and understand that you have no facts but love to claim so anyway. EP

To: fyo who wrote (60730)	6/6/1999 8:26:00 PM
From: grok	Respond to of 1572946

RE: <Fact: The K7 will use an external 2.5V supply. Fact: The K7 will regulate this down to 1.6V internally.> Well, one out of two ain't bad.

To: fyo who wrote (60730)	6/7/1999 12:47:00 AM
From: Paul Engel	Read Replies (3) \| Respond to of 1572946

FYO - Re: "Fact: The K7 will use an external 2.5V supply. Fact: The K7 will regulate this down to 1.6V internally" Thanks. I read the same thing 4 months ago in the AMD ISSCC paper. 1999 International Solid-State Circuits Conference MP 5.4 A 7th-Generation x86 Microprocessor Steven Hesley, Victor Andrade, Bob Burd, Greg Constant, Jeffrey Correll, Matthew Crowley, Michael Golden, Nancy Hopkins, Saiful Islam, Scott Johnson, Rabbani Khondker, Dirk Meyer, Jerry Moench, Hamid Partovi, Randy Posey, Fred Weber, John Yong Advanced Micro Devices, Austin, TX "The phase-locked loop (PLL) operates with a 2.5V supply, inter-nally regulated down to 1.6V to satisfy oxide voltage stress limits. A high precision bandgap circuit minimizes variation of this internal supply voltage. Given the limited voltage headroom and the high frequency target, the PLL is designed to maximize the voltage controlled oscillator (VCO) control range. To ensure minimum static phase error over the maximum VCO control voltage range, the charge pump is designed to regulate the UP current level based on the DOWN level. This avoids large current mismatches when the UP current source devices begins to exit saturation. The cycle compression (less than 25ps) is optimized at the expense of accumulated phase error (less than 1ns) by setting the loop natural frequency low." Paul