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To: Meathead who wrote (83034)	6/7/1999 10:26:00 PM
From: Elmer	Respond to of 186894

Re: "Why would Timna need a processor (FSB) bus? With this level of integration, all Timna needs is Hublink for ICH interface." You're right! No FSB EP

To: Meathead who wrote (83034)	6/7/1999 11:53:00 PM
From: Tenchusatsu	Respond to of 186894

<Why would Timna need a processor (FSB) bus? With this level of integration, all Timna needs is Hublink for ICH interface.> Timna has no processor bus (FSB). The article is wrong. Timna will have two interfaces to the outside world. The first is, of course, the RDRAM memory controller (so much for the anti-Rambus crowd). The secord, I think, is the HubLink interface you mentioned to connect to the "South Bridge" part of the chipset. HubLink is going to be the standard inter-chip communication protocol for Intel's future chipsets. Tenchusatsu

To: Meathead who wrote (83034)	6/8/1999 12:13:00 AM
From: Paul Engel	Respond to of 186894

Meathead - Re: "Why would Timna need a processor (FSB) bus? " The CPU needs a CLOCK - and the FSB (Front Side Bus) is sometimes used to refer to THIS CLOCK - The CLOCK input to the CPU - which is then multiplied internally inside the CPU. A front Side Bus won't be strictly necessary with the Timna - but the CLOCK will be ! For external main memory, the FSB Clock is generally assumed to be the Synchronous CLOCK for the main SDRAM memory , although multiples (or fractional multiples) of the FSB can be used to drive the external SDRAM - or RAMBUS in the case of Timna and Camino. Paul