Very nice read.....RMBS mention....from CMPNet (Semi Biz news)
Debate still rages over aggressive roadmap
By Jack Robertson
WASHINGTON -- Just how aggressive should the industry's technology roadmap be? That question is being debated now as work begins on the document's 1999 update. Some companies are pushing for a more aggressive roadmap. U.S. microprocessor and logic leaders -- Intel Corp., in particular -- want to speed the pace of technology to make it harder for competitors to keep up, according to some chip industry observers.
Proposals are now being considered for the 1999 update that would vary the accelerated pace of microprocessor and DRAM technologies during the next decade. The idea would be to speed up the technology generations for microprocessors at a faster rate than memories, which in recent years have begun to lag MPUs in moving to smaller feature sizes.
This would be a compromise of sorts, however, since proposals already on the table call for the updated roadmap to accelerate chip technology nodes to two-year cycles instead of the current three-year periods. The new roadmap is due out by the end of the year.
Leading-edge logic-chip and microprocessor suppliers are pushing for a more aggressive two-year cycle in the 1999 International Technology Roadmap for Semiconductors, while it is mostly the non-U.S. DRAM makers that want to keep the pace at three years (see story in the April publication).
For now, the roadmap committees have decided to put the next two technology nodes (0.13- and 0.10-micron feature sizes) on two-year cycles. That would mean leading-edge products in those generations would move into production during 2001 and 2003, respectively. The recently published 1998 revision to the roadmap moved up each of those generations by one year but had kept them on three-year cycles -- at 2002 and 2005.
But the debate has shifted. Should DRAM products be aimed to hit the new 1999 roadmap draft targets or should memory technology nodes be less aggressive? asks Alex Oscilowski, chief operating officer of the Sematech. The semiconductor consortium is working on the update of the international roadmap along with the document's main sponsor, the U.S. Semiconductor Industry Association (SIA).
"There is some debate on the 130-nanometer node as to whether or not DRAM and logic will be on the same schedule," acknowledges Oscilowski. Placement of the 0.10-micron node hasn't been resolved completely yet either, he adds. A broader debate continues too on whether the technology generations over the next decade need to be fixed at two-year cycles or kept at three years because of uncertainty over device structures, fab equipment, and processes -- mostly photolithography.
"The debate is still going on," acknowledges Oscilowski, "and the San Francisco workshop [slated for July 8 and 9, prior to the start of the Semicon West trade show] will provide an opportunity for input from international representatives."
Others involved in the drafting of the 1999 update see growing support for moving logic generations at a faster two-year cycle and ahead of DRAM nodes. "There's still a lot of deliberations [to come] before any conclusions can be reached," cautions Juri Matisoo, vice president of technology programs at the SIA. "But it's clear," he adds, "that microprocessor and logic companies are the most aggressive technology drivers today [and who are] the most optimistic that accelerated technical milestones can be met."
In the 1997 update of the U.S. semiconductor roadmap, microprocessors for the first time were elevated to co-driver of chip technologies along with DRAMs. The move was recognition that the two products were driving chip technologies on a range of slightly different fronts.
While MPU generations were described with slightly smaller drawn-gate lengths and DRAMs with half-pitch feature sizes, new technology generations for both products remained in sync in the 1998 roadmap. Logic-driving processors, however, have been targeted with faster production ramp rates than DRAMs in each generation of the roadmap.
Most memory makers are fighting to keep the 0.13-micron technology node for 4-megabit DRAMs at the 2002 timeframe, as it was set in the 1998 revision. "They simply cannot afford a two-year cycle," observes analyst G. Dan Hutcheson, president of VLSI Research Inc. in San Jose.
The roadmap and the efforts to split up DRAMs and microprocessor technologies simply reflects reality, the analyst says. "It's looking in the rearview mirror in a major way," he quips. DRAMs also are beginning to integrate high-performance logic - such as Rambus Inc.'s architecture for high-speed memories, Hutcheson notes.
The roadmap recently has gone through several changes. Last year, the SIA modified the format of what had been a U.S. technology document to include input from international chip makers. And what was supposed to be a minor adjustment to the 1997 update turned into a major revision, moving up technology nodes by a year in recognition that device shrinks had accelerated to a two-year pace in the late '90s (see story in the Jan. 15 publication).
The official release of the 1998 revision was delayed until April of this year. Sources disagree over the reason for the late release. Some blame the difficulties of collecting the final inputs from chip makers around the world, while others say the SIA was late in posting the roadmap's Web site: (http:// www.itrs.net/ntrs/publntrs.nsf).
Despite the expansion of the document from U.S. to global technology, the SIA remains in full control of drafting the roadmap and its updates. The SIA Roadmap Technical Working Group met in Austin, Tex., in early June to take a first cut at a draft of the 1999 update. That document is expected to be presented to the international roadmap group in early July. The group's input then will be used to produce a final draft for review. SIA drafters then will meet again in the fall to come up with a preliminary version of the 1999 roadmap, which will be released publicly for comments. The finished roadmap is expected to be released in late December or early next year, according to the SIA.
While the SIA opened up its roadmap to worldwide participation, the U.S. trade group continues to review the way that it is collecting international input. In fact, the SIA board of directors still view the international process "as an experiment," according to sources at the trade group. The board is slated to vote later this year on whether or not to continue or modify international roadmap procedures.
There also is a wide range of other issues. One concerns the structure of transistor gates at the 100-nm (0.10-micron) node, notes Sematech's Oscilowski. "Are we still going to have polyelectrodes or will the gate material potentially change?" he wonders. "There is also a lithography question," he adds. "What type of exposure will be needed to create the 100-nm structures?"
The 1998 roadmap revision points to a major challenge at 0.10-micron. It indicates there is no known solution as yet to achieve the target of 3,500-MHz on-chip RZ (return-to-zero) clock rates for 0.10-micron logic devices. For resist at this 0.10-micron node, the liquid defect particle size of 50-nm also has no know solutions. The same type of problem is indicated for the earlier 0.13-micron generation devices.
But the 1998 revision does set up a range of new targets for chip making that go into the next century. For the first time, the roadmap sets a long-distance target for DRAM makers to begin production of 1-terabit memories in 2014 using 0.035-micron processes. Now that's a target.
--Additional reporting by J. Robert Lineback
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